Semiconductor Devices and Logic Gates

Current amplification (CE)

$ \begin{aligned} & =\beta=\frac{\Delta I_C}{\Delta I_B} \\ \Rightarrow \Delta I_B & =\frac{\Delta I_C}{\beta} \Rightarrow \Delta I_B=\frac{2.43}{80} \mathrm{~mA} \\ & =0.030 \mathrm{~mA}=30 \times 10^{-6} \mathrm{~A} \end{aligned} $

or $30 \mu \mathrm{~A}$

Negative feedback counteract the changes of output signal.

As frequent charges are depressed, there is low noise and distortion in output.

At absolute zero temperature (0 Kelvin), there is no thermal energy available.

1. Semiconductors and Energy Bands: In a semiconductor, electrons reside in the valence band at lower energy levels. For conduction to occur, electrons need to jump from the valence band to the conduction band, leaving behind holes in the valence band. The energy required for this jump is called the band gap energy.

2. Effect of Temperature:

   • At typical room temperatures, some electrons gain enough thermal energy to cross the band gap and move into the conduction band, contributing to electrical conductivity.

   • As temperature decreases, the number of thermally excited electrons decreases.

   • At absolute zero temperature (0 K), there is no thermal energy. Therefore, no electrons can gain enough energy to jump from the valence band to the conduction band.

3. Result:

   • The valence band remains completely filled.

   • The conduction band remains completely empty.

   • A material with a completely filled valence band and an empty conduction band, separated by a band gap, behaves as an insulator. There are no free charge carriers available for conduction.

Therefore, at absolute zero temperature, a semiconductor behaves like an insulator.

The final answer is $\boxed{D}$

$ A=1, B=0, C=1 $

$ \begin{aligned} y_1 & =\overline{A B}=\overline{1.0} \\ & =\overline{0}=1 \\ y_2 & =\overline{B+C}=\overline{0+1}=\overline{1}=0 \\ y_3 & =y_1 \cdot y_2=1.0=0 \end{aligned} $

From the graph

In region I, output voltage is high as $V_0$ when the input voltage $V_i$ is low. i.e., transistor is off. This is cutoff region.

In region II, output voltage decreases as input voltage increases. This is the

situation when transistor operates as an amplifier.

Thus, in region II, transistor is in active mode.

In region III, output voltage is low when input voltage is high i.e., maximum current flow through the collector. Thus, transistor is in saturation region.

NAND and NOR gate are knows as universal gate because any logic gate can be implemented using these two gates.

To use transistor as a switch in a common emitter configuration, the transistor operates in cutoff and saturation region.

In cutoff region, the transistor is "off" and acts like an open switch, allowing no current to flow between the collector and emitter.

In saturation region, the transistor is "on" and acts like a closed switch (short circuit) between the collector and emitter, allowing maximum current to flow.

In active region, transistor works as an amplifier.

$ \begin{aligned} \lambda & =\frac{h c}{E} \\ & =\frac{6.62 \times 10^{-34} \times 3 \times 10^8}{1.9 \times 1.6 \times 10^{-19}} \\ & =6.53 \times 10^{-7} \mathrm{~m} \\ & \simeq 653 \mathrm{~nm} \end{aligned} $

The visible light spectrum ranges approximately 400 nm (violet) to 700 nm (red). A wavelength of 653 nm falls with in the red part of the spectrum. Therefore, the colour of the light emitted by the LED is red.

Given:

• Number of electrons entering emitter per second (or per given time)

  $ N_E = 10^{10} $ electrons in $ t = 0.4 \, \mu s $

• $ 5\% $ of electrons are lost in the base.

So, only $ 95\% $ of electrons reach the collector.

Step 1: Find the emitter current

Total charge entering emitter in $ 0.4 \, \mu s $:

$ Q_E = N_E \times e = 10^{10} \times 1.6 \times 10^{-19} = 1.6 \times 10^{-9} \, C $

Emitter current:

$ I_E = \frac{Q_E}{t} = \frac{1.6 \times 10^{-9}}{0.4 \times 10^{-6}} = 4.0 \, mA $

Step 2: Find the collector current

Since $ 5\% $ are lost, $ 95\% $ reach collector:

$ I_C = 0.95 \, I_E = 0.95 \times 4.0 \, mA = 3.8 \, mA $

✅ Final Answer:

$ \boxed{I_C = 3.8 \, mA} $

Correct option: D (3.8 mA)

According to conservation of energy

$ \begin{aligned} & \frac{1}{2} m_e v_i^2=\frac{1}{2} m_e v_f^2+e V_b \\ \Rightarrow \quad & \frac{1}{2} m_e v_f^2=\frac{1}{2} m_e v_i^2-e V_b \\ \Rightarrow \quad & v_f^2=v_i^2=\frac{2 e V_b}{m_e} \\ & =\left(5 \times 10^5\right)^2-\frac{2 \times 1.6 \times 10^{-19} \times 0.4}{9 \times 10^{-31}} \\ & =9 \times 10^{10} \\ \Rightarrow & v_f=\sqrt{9 \times 10^{10}}=3 \times 10^5 \mathrm{~m} / \mathrm{s} \end{aligned} $

Power gain $=$ Current $\times$ Voltage gain

$ \Rightarrow 1800=\text { Current gain }(\beta) \times 60 $

$ \begin{array}{ll} \Rightarrow & \beta=\frac{1800}{60} \Rightarrow \beta=30 \\ \Rightarrow & \frac{\Delta I_C}{\Delta I_B}=30 \Rightarrow \frac{\Delta I_B-\Delta I_B}{\Delta I_B}=30 \\ \Rightarrow & \frac{\Delta I_E}{\Delta I_B}-1=30 \\ \Rightarrow & \frac{0.62}{\Delta I_B}=31 \\ \Rightarrow & \Delta I_B=\frac{0.62}{31}=0.02 \mathrm{~mA} \\ \therefore & \Delta I_C=\Delta I_E-\Delta I_B=0.62-0.02 \\ & =0.60 \mathrm{~mA} \end{array} $

$ \begin{aligned} & y_1=\overline{1+1}=\overline{1}=0 \\ & y_2=\overline{1+1}=\overline{1}=0 \\ & y_3=y_1 \cdot y_2=0.0=0 \end{aligned} $

Transistor Transistors are commonly used as amplifiers to increase the amplitude of a signal.

(b) Diode Diode are used in rectifier circuits to convert

alternating current $ (\mathrm{AC}) $ to direct current (DC).

(c) Zener diode Zener diodes are used in voltage regulator circuits to maintain a constant voltage.

(d) Capacitor Capacitors are used in filter circuits to smooth out fluctuations in voltage by filtering out noise.

So, the correct matching is Transistor : Amplifier Diode : Rectified Zener diode : Voltage regulator Capacitor : Filter circuit

From left side, the first gate is OR gate and next one is AND gate. So, the outpur of OR gate is $ A+B $ and the output of AND gate $ Y=(A+B) \cdot C $. We know that, for AND gate, the output will be 1 if both inputs are 1 . So,

$ A+B=1 \text { and } C=1 $

For $ A+B=1 $, either of the inputs must be one.

Therefore, from the given option (c) is the correct answer.

$ A=1, B=0 \text { and } C=1 $

An $n$-type semiconductor, after being doped with donor atoms, has electrons as the majority charge carriers. However, the semiconductor remains electrically neutral overall.

Here's why:

Initially, the semiconductor material is intrinsically neutral, with an equal number of protons (positive charge) and electrons (negative charge).

Doping introduces donor atoms, which have more electrons than necessary to form bonds with the host atoms. These extra electrons become free carriers.

Despite the increased number of free electrons, the donor atoms themselves are neutral because they provide one more electron in their outer shell but don’t remove the existing positive charges in the nucleus.

Thus, even though there is an excess of free electrons compared to holes, the $n$-type semiconductor as a whole is charge neutral because the additional electrons are matched by the additional positive charge in donor atom's nucleus.

Therefore, the answer is:

Option C: neutral

In the output voltage versus input voltage graph of a transistor, the region where a transistor can be used as an amplifier is the active region (Option A).

In the active region, the transistor acts as a linear amplifier. The base-emitter junction is forward-biased, and the collector-base junction is reverse-biased. This configuration allows the transistor to amplify small input signals into larger output signals while maintaining proportionality and phase characteristics.

Explanation:

Active Region:

Base-Emitter Junction: Forward-Biased

Collector-Base Junction: Reverse-Biased

Used for Amplification

Proportional relationship between input and output voltage

Cut-off Region (Option B):

Both junctions are reverse-biased.

The transistor is off, and no current flows between collector and emitter.

Saturation Region (Option C):

Both junctions are forward-biased.

The transistor is fully on, allowing maximum current to flow between collector and emitter.

Not suitable for amplification as it works like a closed switch.

Passive Region (Option D):

This term is not typically used in the context of transistor operation regions.

Therefore, the active region is crucial for the amplification function of transistors.

Given,

Voltage gain $ =160=\frac{V_{\text {out }}}{V_{\text {in }}} $

$ I_{C}=\text { ? } $

Base current, $ I_{B}=100 \mu \mathrm{~A} $

Load resistance, $ R_{L}=4 \mathrm{k} \Omega $

Input resistance, $ R_{I}=1 \mathrm{k} \Omega $

Voltage gain $ =\beta \frac{R_{L}}{R_{I}} $

where $ \beta $ is current gain

$ \begin{aligned} \beta & =\frac{I_{C}}{I_{B}} \\\\ 160 & =\frac{I_{C}}{I_{B}} \cdot \frac{R_{L}}{R_{I}} \\\\ 160 & =\frac{I_{C}}{100 \mu \mathrm{~A}} \cdot \frac{4 \mathrm{k} \Omega}{1 \mathrm{k} \Omega} \\\\ I_{C} & =4 \times 10^{-3} \mathrm{~A} \\\\ I_{C} & =4 \mathrm{~mA} \end{aligned} $

The presence of the capacitor across the output terminal of rectifier eliminates the pulsation and fluctuation in the output voltage. The capacitor hold charge during the charging phase and discharging slowly during the discharging phase, maintaing relative constant voltage across load.

Given, $V_z=30 \mathrm{~V}, V_{\max }=100 \mathrm{~V}$

Voltage drop across zener branch and its parallel branch will be the same i.e.,

Current in $6 \mathrm{k} \Omega$ resistor,

$ i_1=\frac{30 \mathrm{~V}}{6 \mathrm{k} \Omega}=5 \mathrm{~mA} $

Current through rest of resistor $=\frac{V-V_z}{R_z}$

$ \begin{aligned} & =\frac{70 \mathrm{~V}}{7 \mathrm{k} \Omega}=10 \mathrm{~mA} \\\\ \therefore I_{\text {mener }} & =10 \mathrm{~mA}-5 \mathrm{~mA}=5 \mathrm{~mA} \end{aligned} $

From diagram

$ \begin{aligned} & Y_1=\overline{A \cdot(\overline{A+B})} \\\\ & Y_2=\overline{A+B} \end{aligned} $

Truth table,

In an intrinsic semiconductor, the concentration of electrons ($n_i$) and holes ($p_i$) are equal and given by:

$ n_i = p_i = 6 \times 10^{15} \, \mathrm{m}^{-3}. $

When the semiconductor is doped with an impurity, the electron concentration increases to $4 \times 10^{22} \, \mathrm{m}^{-3}$, which is denoted by $n$. The product of the electron concentration ($n$) and the hole concentration ($p$) in a semiconductor at thermal equilibrium is given by:

$ n \cdot p = n_i^2. $

To find the hole concentration ($p$) in the doped semiconductor, use the above relationship:

Calculate $n_i^2$:

$ n_i^2 = (6 \times 10^{15} \, \mathrm{m}^{-3})^2 = 36 \times 10^{30} \, \mathrm{m}^{-6}. $

Using the relation $n \cdot p = n_i^2$, solve for $p$:

$ p = \frac{n_i^2}{n} = \frac{36 \times 10^{30} \, \mathrm{m}^{-6}}{4 \times 10^{22} \, \mathrm{m}^{-3}}. $

Calculate $p$:

$ p = \frac{36}{4} \times 10^{30 - 22} \, \mathrm{m}^{-3} = 9 \times 10^8 \, \mathrm{m}^{-3}. $

Therefore, the concentration of holes in the doped semiconductor is $9 \times 10^8 \, \mathrm{m}^{-3}$, which corresponds to Option C.

Given, inputs are

$ A=1 \Rightarrow B=1 $

NOR GATE

When inputs $A=1$ and $B=1$, then NOR gate will gives output of $X_1=0$

AND GATE

When inputs $A=1$ and $B=0$, then AND gate will gives output of $Y_1=0$.

OR GATE

When inputs $A=0$ and $B=1$, then gate wil gives output of $Y_2=1$

Thus, value of $Y_1=0$ and $Y_2=1$.

When an $n$-type semiconductor is heated, thermal energy generates additional electron–hole pairs.

• Each time an electron–hole pair is generated, one electron and one hole are produced.

• So, the increase in the number of electrons and holes due to heating is equal.

Hence, on heating an $n$-type semiconductor, the number of holes and electrons increases equally.

Correct option: D

For AND gate $D_1$ out put will be $=X \cdot \bar{Y}$

For AND gate $D_2=\bar{X} \cdot Y$

For AND gate $D_3=D_1 \cdot D_2$

$ =(X \cdot \bar{Y})(\bar{X} \cdot Y)=0 $

Now writing truth table

$ \begin{array}{ccc} \hline \boldsymbol{A} & \boldsymbol{B} & \boldsymbol{Y} \\ \hline 0 & 0 & 0 \\ \hline 1 & 0 & 0 \\ \hline 0 & 1 & 0 \\ \hline 1 & 1 & 0 \\ \hline \end{array} $

Hence, option (a) is correct.

Photo-diode is a device which is reverse biased and produced current when light falls on it.

When photo-diode is reverse biased, the width of depletion layer increases and a small reverse current flows through diode.

When light falls on junction, electron-holes pair are generated in big number and these charge carriers can

easily cross the barrier. Due to reverse bias, and broad depletion layer photocurrent is significant in reverse bias even for fractional change in minority carriers.

So, option (c) is the correct option.

LED-Light emitting diode.

It is connected in forward biased. The band width of light is $10-50 \mathrm{~nm}$. No warm up time is required for LED to start.

It require very low voltage to operate. It can switch ON and OFF very quickly because very low energy required for excitation and rapidly releases this energy.

So, option (d) is correct option.

From the given logic circuit diagram

$ \begin{aligned} & & P & =\bar{X}+Y=X \cdot \bar{Y} \\ & & Q & =\overline{X \bar{Y}}=\bar{X}+\bar{Y} \\ \Rightarrow & & Q & =\bar{X}+Y \\ \text { and } & & R & =\overline{P+Q} \end{aligned} $

Where, $X=1$ and $Y=1$, then

$ \begin{aligned} & P=1 \cdot \overline{1}=1 \cdot 0=0 \\ & Q=\bar{X}+Y=\overline{1}+1=0+1=1 \\ & and\,\,\,R=\overline{P+Q}=\overline{0+1}=\overline{1}=0 \end{aligned} $

The given symbol represents $n-p-n$ transistor.

In common emitter amplifier, output voltage is $180^{\circ}$ out of phase of input voltage.

$ \begin{aligned} &\text { Effective barrier height }\\ &\begin{aligned} & =\text { barrier potential - applied voltage } \\ & =0.7 \mathrm{~V}-0.3 \mathrm{~V} \\ & =0.4 \mathrm{~V} \end{aligned} \end{aligned} $

The ratio of electron to hole current is:

$ \frac{I_e}{I_h} = \frac{7}{4} $

The ratio of the drift velocities of electrons to holes is:

$ \frac{v_{de}}{v_{dh}} = \frac{5}{4} $

In semiconductors, the drift current ($ I $) is proportional to the product of the charge carrier concentration ($ n $) and the drift velocity ($ v_d $). This relationship is expressed as:

$ I \propto n \cdot v_d $

Thus, for electron and hole currents, we can write:

$ I_e \propto n_e \cdot v_{de} $

$ I_h \propto n_h \cdot v_{dh} $

By dividing the expression for electron current by the expression for hole current, we get:

$ \frac{I_e}{I_h} = \frac{n_e \cdot v_{de}}{n_h \cdot v_{dh}} $

Substituting in the given ratios:

$ \frac{n_e}{n_h} = \frac{I_e \cdot v_{dh}}{I_h \cdot v_{de}} $

$ \frac{n_e}{n_h} = \frac{7}{4} \cdot \frac{4}{5} = \frac{7}{5} $

Thus, the ratio of the concentration of electrons to holes is $ \frac{7}{5} $ or $ 7:5 $.

Intrinstic semiconductor are those material where the charge carrier (holes and electrons) are in equal number.

Donor impurity will provide its excess electron to other atom of crystal structure.

Hence, when a semiconductor is doped with a donor impurities, it will increase the concentration of electron and at the same time decreases the holes. Concentration by favouring electron-holes pairing.

In a transistor, the currents are related by specific equations. Here's how to determine the collector current when the base and emitter currents are known:

Base current ($I_b$): $10 \, \mu \mathrm{A}$

Emitter current ($I_e$): $1 \, \mathrm{mA}$ = $1000 \, \mu \mathrm{A}$

In a transistor, the relationship between the currents is defined by the equation:

$ I_e = I_c + I_b $

Where $ I_c $ is the collector current. To find the value of $ I_c $, rearrange the equation:

$ I_c = I_e - I_b $

Substitute the given values:

$ \begin{aligned} I_c &= 1000 \, \mu \mathrm{A} - 10 \, \mu \mathrm{A} \\ &= 990 \, \mu \mathrm{A} \end{aligned} $

Thus, the collector current is $990 \, \mu \mathrm{A}$.

Output of NAND gate = Input of NOT gate

So, the output will be an AND gate.

Given, band gap in semiconductor material,

The given logic circuit diagram is shown as

Output of above logic gate is given as

$ \begin{array}{rlr} Y & =\overline{\bar{A} \cdot \bar{B}} & \text { [By de Morgan's law } \\ & =\overline{\bar{A}}+\overline{\bar{B}} & \overline{x \cdot y}=\bar{x}+\bar{y} \\ & =A+B & \because \overline{\bar{x}}=x] \\ & =\text { Output of OR gate } & \end{array} $

$ \begin{aligned} &\text { Band gap, }\\ &\begin{aligned} & E_g=2.8 \mathrm{eV} \\ &=2.8 \times 1.6 \times 10^{-19} \mathrm{~J} \\ & \Rightarrow \quad \frac{h c}{\lambda}=2.8 \times 1.6 \times 10^{-19} \\ &\,\,\,\,\,\,\, \,\,\,\,\,\,\, \,\,\,\,\,\,\, \,\,\,\,\,\,\, \,\,\,\,\,\,\, \,\,\,\,\,\,\, \,\,\,\,\,\,\, \,\,\,\,\,\,\, \quad\left[\because E_g=\frac{h c}{\lambda}\right] \\ & \Rightarrow \frac{6 \times 10^{-34} \times 3 \times 10^8}{\lambda}=2.8 \times 1.6 \times 10^{-19} \end{aligned} \end{aligned} $

$ \begin{aligned} & \Rightarrow \quad \frac{1.8 \times 10^{-25}}{\lambda}=4.48 \times 10^{-19} \\ & \Rightarrow \quad \lambda=\frac{1.8 \times 10^{-25}}{4.48 \times 10^{-19}} \\ & \quad=0.4018 \times 10^{-6} \mathrm{~m} \\ & \quad=401.8 \times 10^{-9} \mathrm{~m} \\ & \quad=401.8 \mathrm{~nm} \end{aligned} $

Hence, approximate wavelength which can detect by $p-n$ junction is less than 401.8 nm .

Therefore, wavelength of 600 nm cannot be detected by $p-n$ junction.

The given logic circuit is represented as

The output of logic gate is

$ Y=\overline{\bar{A}+\bar{B}}=\overline{\bar{A}} \cdot \overline{\bar{B}}=A \cdot B $

[By de Morgan's law, $\overline{x+y}=\bar{x} \cdot \bar{y}$ ]

= Output of AND gate

Given, number of silicon atom,

$ n_{\mathrm{Si}}=5 \times 10^{28} \text { atoms } / \mathrm{m}^3 $

Number of arsenic atom,

$ \begin{aligned} n_{\mathrm{As}} & =4.5 \times 10^{21} \text { atom } / \mathrm{m}^3 \\ n_i & =1.5 \times 10^{16} / \mathrm{m}^3 \end{aligned} $

Number of free electrons obtained from

$ \begin{aligned} \text { doping } & =n_e \\ & =n_{\mathrm{As}} \\ & =4.5 \times 10^{21} \text { electrons } / \mathrm{m}^3 \end{aligned} $

∴ Total number of electrons after doping,

$ \begin{aligned} N & =n_e+n_i \\ & =4.5 \times 10^{21}+1.5 \times 10^{16} \\ & =1.5 \times 10^{16}\left(3 \times 10^5+1\right] \\ & =1.5 \times 10^{16}\left(3 \times 10^5\right) \\ & =4.5 \times 10^{21} \end{aligned} $

$ \begin{aligned} &\text { According to mass-action law, }\\ &\begin{aligned} n_e \cdot m_h & =n_i^2 \\ n_h & =\frac{n_i^2}{n_e} \\ & =\frac{\left(1.5 \times 10^{16}\right)^2}{4.5 \times 10^{21}} \\ & =\frac{225 \times 10^{32}}{4.5 \times 10^{21}} \\ \Rightarrow \quad n_h & =5 \times 10^{10} \mathrm{holes} / \mathrm{m}^3 \\ \therefore \quad \frac{n_e}{n_h} & =\frac{4.5 \times 10^{21}}{5 \times 10^{10}} \\ & =0.9 \times 10^{11} \\ & =9 \times 10^{10} \end{aligned} \end{aligned} $

The given logic circuit diagram is

Output of the given logic gate is

$ \begin{aligned} Y & =\overline{A B} \\ & =\text { Output of NAND gate } \end{aligned} $

Dynamic resistance, $r_d=d V / d I$

Now, $I=I_0\left(e^{V / 2 V_T}-1\right)$

$ \begin{aligned} & \Rightarrow \frac{d I}{d V}=I_0\left(e^{V / 2 V_T} \cdot \frac{1}{2 V_T}\right) \\ & \Rightarrow \frac{d V}{d I}=\frac{2 V_T}{I_0} \cdot e^{\frac{V}{2 V_T}} \Rightarrow r_d=\frac{2 V_T}{I_0 \cdot e^{V / 2 V_T}} \end{aligned} $

Now, when $I=1000 I_0$, from Eq. (i) we get

$ \begin{aligned} & & I_0 \cdot 1000 & =I_0\left(e^{\frac{V}{2 V_T}}-1\right) \\ \Rightarrow & & e^{\frac{V}{2 V_T}} & =1001 \end{aligned} $

And at $I=10 I_0$,

$ e^{\frac{V}{2 V_T}}=11 $

Now, $r_d$ at $I=1000 I_0$

$ =\frac{2 V_T}{I_0} \times \frac{1}{1001} $

And $r_d$ at $I=10 I_0=\frac{2 V_T}{I_0} \times \frac{1}{11}$

Given, $r_d\left(I=1000 I_0\right)$

$ \begin{array}{rlrl} & =\alpha \cdot r_d\left(I=10 I_0\right) \\ \Rightarrow & \frac{2 V_T}{I_0} \times \frac{1}{1001} =\alpha \cdot \frac{2 V_T}{I_0} \times \frac{1}{11} \\ \Rightarrow & \alpha=\frac{11}{1001}=\frac{1}{91} \approx \frac{1}{100} \end{array} $

In a $n-p-n$ transistor, emitter region is highly doped, collector region is moderately doped and base region is lightly doped.

The given logic circuit diagram is drawn as,

The output of logic circuit is given as,

$ \begin{aligned} X & =A B+(A+B)=A B+A+B \\ & =A(B+1)+B \\ & =A \cdot 1+B\,\,\,\,\,\,\,\,\,\,\, [\because B+1=1]\\ & =A+B \\ & =\text { output of OR gate. } \end{aligned} $

When trivalent impurities ( $\mathrm{Al}, \mathrm{Ga}$, B etc.) are doped in a pure semiconductor material ( Ge or Si ), then $p$-type semiconductor is formed. In $p$-type semiconductor holes are majority charge carriers and electrons are minority charge carriers.

The truth table of NAND gate is given as

$ \begin{array}{cccc} \hline \boldsymbol{A} & \boldsymbol{B} & \boldsymbol{A} \boldsymbol{B} & \boldsymbol{Y}=\overline{\boldsymbol{A} \boldsymbol{B}} \\ \hline 0 & 0 & 0 & 1 \\ \hline 0 & 1 & 0 & 1 \\ \hline 1 & 0 & 0 & 1 \\ \hline 1 & 1 & 1 & 0 \\ \hline \end{array} $

∴ Hence, it is clear from truth table, when $A=1, B=1 ; Y=0$

In $p-n-p$ transistor the collector current is slightly less than emitter current because the emitter-base junction is forward biased, so the majority charge carries (holes) of

emitter get replaced from the positive terminal and move towards base. As, base is lightly dopped, some of the holes combine with the majority charge carries electrons present in the base and most of the holes reach the collector, crossing the collector-base junction. So, current in the circuit is $I_E=I_B+I_C$

The Boolean expression of NOR gate is

$ Y=\overline{A+B} $

where, $A$ and $B$ are inputs and $Y$ is the output.

Truth table of NOR gate is

$ \begin{array}{ccc} \hline \boldsymbol{A} & \boldsymbol{B} & \boldsymbol{Y}=\overline{\boldsymbol{A}+\boldsymbol{B}} \\ \hline 0 & 0 & 1 \\ \hline 0 & 1 & 0 \\ \hline 1 & 0 & 0 \\ \hline 1 & 1 & 0 \\ \hline \end{array} $

Hence, when all inputs ( $A$ and $B$ ) are low ( 0 ), then output of NOR gate is high (1).

$ \text { In option (a) } $

where, $D=A \cdot \bar{B}+\bar{A} \cdot B$

Put $A=1$ and $B=1$,

then $D=1 \cdot \overline{1}+\overline{1} \cdot 1=1 \cdot 0+0 \cdot 1=0+0=0$

So, this option is wrong.

In option (b)

$ \begin{aligned}where,\,\, D & =[\overline{[(\bar{A}+B)+(A+\bar{B}]} \\ & =[\overline{(\bar{A}+A)+(B+\bar{B})}] \end{aligned} $

$ \begin{aligned} & \text { } \begin{aligned}Put\,\, A & =1 \text { and } B=1, \\ \text { then } D & =[(\overline{1+1}+(1+\overline{1}) \\ & =[\overline{(0+1)+(1+\overline{0})}]=\overline{[1+1]}=\overline{[1]}=0 \end{aligned} \end{aligned} $

So, this option is wrong.

In option (c)

where, $D=(A+B) \cdot(\bar{A}+\bar{B})$

$ \begin{aligned} & =A \cdot \bar{A}+A \cdot \bar{B}+B \cdot \bar{A}+B \cdot \bar{B} \\ & =0+A \cdot \bar{B}+B \cdot \bar{A}+0=A \cdot \bar{B}+\bar{A} \cdot B \end{aligned} $

Put $A=1$ and $B=1$,

$ \text { } \begin{aligned} then\,\, D & =1 \cdot \overline{1}+\overline{1} \cdot 1 \\ & =1 \cdot 0+0 \cdot 1=0+0=0 \end{aligned} $

So, this option is wrong.

In option (d)

where, $D=A \cdot B+\bar{A} \cdot \bar{B}$

Put $A=1$ and $B=1$,

Given, base current in $n-p-n$ transistor,

$ I_B=2 \mathrm{~mA}=2 \times 10^{-3} \mathrm{~A} $

Since, $95 \%$ of emitted electrons reach the collector, hence Collector current,

$ \begin{equation*} I_C=95 \% \text { of } I_E \Rightarrow I_C=0.95 I_E \Rightarrow I_E=\frac{I_C}{0.95} \,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,...(i) \end{equation*} $

But we know that, $I_E=I_C+I_B$

$ \Rightarrow \quad \frac{I_C}{0.95}=I_C+2 \times 10^{-3} \Rightarrow \frac{I_C}{0.95}-I_C=2 \times 10^{-3} $

The circuit given is as shown

Potential drop across

$ R_L=V_L=V_Z=10 \mathrm{~V} $

Potential drop across $4 \mathrm{k} \Omega$ resistance is

$ V_R=60-10=50 \mathrm{~V} $

Current through $4 \mathrm{k} \Omega$ resistance is

$ I=\frac{V_R}{R}=\frac{50}{4 \times 10^3}=12.5 \times 10^{-3} $

$\mathrm{A}=12.5 \mathrm{~mA}$

Current through load resistance $=I_L$

$ =\frac{V_L}{R_L}=\frac{10}{2 \times 10^3}=5 \mathrm{~mA} $

Also, $I_Z=I-I_L=12.5-5=7.5 \mathrm{~mA}$