Semiconductor Devices and Logic Gates
The current amplification factor of a transistor in common emitter configuration is 80 . If the emitter current is 2.43 mA , then the base current is
$15 \mu \mathrm{~A}$
$1.5 \mu \mathrm{~A}$
$3 \mu \mathrm{~A}$
$30 \mu \mathrm{~A}$
The negative feedback in an amplifier
increases noise and distortion.
reduces noise and distortion.
reduces noise and increases distortion.
increases noise and reduces distortion.
At absolute zero temperature, a semiconductor behaves like
semiconductor
superconductor
conductor
insulator
Three logic gates are connected as shown in the figure. If the inputs are $A=1, B=0$ and $C=1$, then the values of $y_1, y_2$ and $y_3$ respectively are

1, 0, 0
$0,1,0$
$1,1,0$
1, 0, 1
The graph between the input voltage $\left(V_i\right)$ and the output voltage ( $V_o$ ) of a transistor connected in common emitter configuration is shown in the figure. The active, saturation and cutoff regions of the transistor are respectively

I, II and III
II, III and I
I, III and II
III. I and II
Which of the following logic gates is a universal gate?
AND
$O R$
NOT
NAND
According to a graph drawn between the input and output voltages of a transistor connected in common emitter configuration, the region in which transistor acts as a switch is
cutoff or saturation region
active region
active or saturation region
cutoff or active region
If the energy gap of a semiconductor used for the fabrication of an LED is nearly 1.9 eV , then the color of the light emitted by the LED is
white
red
green
blue
$10^{10}$ electrons enter the emitter of a junction transistor in a time of $0.4 \mu \mathrm{~s}$. If $5 \%$ of the electrons are lost in the base, then the collector current is
3.0 mA
3.2 mA
3.6 mA
3.8 mA
An electron in $n$-region of a $p-n$ junction moves towards the junction with a speed of $5 \times 10^5 \mathrm{~ms}^{-1}$. If the barrier potential of the junction is 0.45 V , then the speed with which the electron enters the $p$-region after penetration through the barrier is
(Charge of the electron $=1.6 \times 10^{-19} \mathrm{C}$ and mass of the electron $=9 \times 10^{-31} \mathrm{~kg}$ )
$3 \times 10^5 \mathrm{~ms}^{-1}$
$5 \times 10^5 \mathrm{~ms}^{-1}$
$4 \times 10^5 \mathrm{~ms}^{-1}$
$6 \times 10^5 \mathrm{~ms}^{-1}$
The power gain and voltage gain of a transistor connected in common emitter configuration are 1800 and 60 respectively. If the change in the emitter current is 0.62 mA , then the change in the collector current is
0.60 mA
0.58 mA
0.52 mA
0.48 mA
Six logic gates are connected as shown in the figure. The values of $y_1, y_2$ and $y_3$ respectively are
$(0,1,0)$
$(1,0,0)$
$(0,0,1)$
$(0,0,0)$
At absolute zero temperature, an intrinsic semiconductor behaves as
conductor
superconductor
insulator
intrinsic semiconductor
The logic gate equivalent to the combination of logic gates shown in the figure is
AND
NOR
$O R$
NAND
In a transistor, if the collector current is $98 \%$ of emitter current, then the ratio of the base and collector currents is
$1: 98$
$1: 1$
$1: 49$
$1: 99$
In the given circuit, if $A=0, B=1$ and $C=1$ are inputs, then the values of $y_1$ and $y_2$ are respectively
1.1
0.1
0.0
1.0
$ \text { In the given options, the diode that is forward biased is } $




In a common emitter transistor amplifier the resistance of collector is $3 \mathrm{k} \Omega$. If the current amplification factor is 100 and the base resistance is $2 \mathrm{k} \Omega$, then the power gain of the transistor is
150
10000
1500
15000
If $X, Y$ and $Z$ are the sizes of the emitter, base and collector of a transistor respectively, then
$X>Z>Y$
$X>Y>Z$
$Z>X>Y$
$Z>Y>X$
The logic gate equivalent to the circuit given in the figure is
NAND
$O R$
AND
NOR
In common emitter amplifier of a transistor, if the ratio of the voltage gain and current amplification factor is 4 , then the ratio of the collector and base resistances is
$16: 1$
$1: 16$
$1: 4$
$4: 1$
If three logic gates are connected as shown in the figure, then the correct truth table of the circuit is
$ \begin{array}{|c|c|c|} \hline A & B & y \\ \hline 0 & 0 & 1 \\ 0 & 1 & 0 \\ 1 & 0 & 0 \\ 1 & 1 & 1 \\ \hline \end{array} $
$ \begin{array}{|c|c|c|} \hline A & B & y \\ \hline 0 & 0 & 1 \\ 0 & 1 & 1 \\ 1 & 0 & 1 \\ 1 & 1 & 0 \\ \hline \end{array} $
$ \begin{array}{|c|c|c|} \hline A & B & y \\ \hline 0 & 0 & 0 \\ 0 & 1 & 0 \\ 1 & 0 & 0 \\ 1 & 1 & 1 \\ \hline \end{array} $
$ \begin{array}{|c|c|c|} \hline A & B & y \\ \hline 0 & 0 & 0 \\ 0 & 1 & 1 \\ 1 & 0 & 1 \\ 1 & 1 & 0 \\ \hline \end{array} $
The voltage gain and the current amplification factor of a transistor in common emitter configuration are 300 and 60 respectively. If the collector resistance is $5 \mathrm{k} \Omega$, then the base resistance is
$5 \mathrm{k} \Omega$
$25 \mathrm{k} \Omega$
$2 \mathrm{k} \Omega$
$1 \mathrm{k} \Omega$
The logic gate equivalent to the circuit shown in the figure is
AND
NAND
NOR
$O R$
When three NAND logic gates are connected as shown in the figure, then the logic gate equivalent to the circuit is
NOT
AND
$O R$
NOR
The device used for voltage regulation is
Zener diode
photo diode
light emitting diode
solar cell
emitter, base, collector
collector, base, emitter
base, emitter, collector
base, collector, emitter
A transistor works as an amplifier when
emitter-base junction is forward biased and base-collector junction is reverse biased.
both emitter-base and base-collector junctions are forward biased.
both emitter-base and base-collector junctions are reverse biased.
emitter-base junction is reverse biased and base-collector junction is forward biased.
If five logic gates are connected as shown in the figure, then the values of $y_1, y_2$ and $y_3$, are respectively
1, 1, 1
$0,0,1$
$1,1,0$
$1,0,1$
A Zener diode of breakdown voltage 20 V is connected as shown in the given circuit. The current through Zener diode is
10 mA
4 mA
6 mA
8 mA
The voltage gains of two amplifiers connected in series are 8 and 12.5 . If the voltage of the input signal is $200 \mu \mathrm{~V}$, then the voltage of the output signal is
$50 \mu \mathrm{~V}$
$20 \mu \mathrm{~V}$
20 mV
50 mV
Match the devices given in List-I with their uses given in List-II.
| List-I | List -II |
| a Transistor | e Filter circuit |
| b Diode | f Voltage regulator |
| c Zener diode | g Rectifier |
| d Capacitor | h Amplifier |
The correct answer is
To get output 1 for the following logic circuit, the correct choice of the inputs is 
A zener diode of zener voltage 30 V is connected in circuit as shown in the figure. The maximum current through the zener diode is

Three logic gates are connected as shown in the figure. If the inputs are $A=1$ and $B=1$, then the values of $Y_1$ and $Y_2$ respectively are
$ \text { The following configuration of gates is equivalent to } $
$ \text { Truth table for the given circuit is } $
$ \begin{array}{lll} \hline A & B & Y \\ \hline 0 & 0 & 1 \\ \hline 0 & 1 & 0 \\ \hline 1 & 0 & 1 \\ \hline 1 & 1 & 1 \\ \hline \end{array} $
$ \begin{array}{lll} \hline A & B & Y \\ \hline 0 & 0 & 1 \\ \hline 0 & 1 & 1 \\ \hline 1 & 0 & 0 \\ \hline 1 & 1 & 1 \\ \hline \end{array} $
$ \begin{array}{lll} \hline A & B & Y \\ \hline 0 & 0 & 1 \\ \hline 0 & 1 & 1 \\ \hline 1 & 0 & 1 \\ \hline 1 & 1 & 1 \\ \hline \end{array} $
$ \begin{array}{lll} \hline A & B & Y \\ \hline 0 & 0 & 0 \\ \hline 0 & 1 & 1 \\ \hline 1 & 0 & 1 \\ \hline 1 & 1 & 1 \\ \hline \end{array} $
If $R_C$ and $R_B$ are respectively the resistances of in collector and base sides of the circuit and $\beta$ is the current amplification factor, then the voltage gain of a transistor amplifier in common emitter configuration is
The current gain of a transistor in common emitter configuration is 80 . The resistances in collector andbase sides of the circuit are $5 \mathrm{k} \Omega$ and $1 \mathrm{k} \Omega$ respectively. If the input voltage is 2 mV , the output voltage is
4 V
0.4 V
0.8 V
8 V
Four logic gates are connected as shown in the figure. If the inputs are $A=0, B=1$ and $C=1$, then the values of $Y_1$ and $Y_2$ respectively, are

$ \begin{aligned} y & =\overline{\bar{A}+\bar{B}}=\overline{\bar{A}} \cdot \overline{\bar{B}}=A B \\ & =\text { Output of AND gate } \end{aligned} $










