Semiconductor Devices and Logic Gates

To find the voltage gain of a common emitter amplifier, we have the following information:

AC current gain ($\beta$) = 40

Input resistance ($R_i$) = $2 \, \mathrm{k}\Omega$

Load resistance ($R_L$) = $10 \, \mathrm{k}\Omega$

The voltage gain ($A_v$) is calculated using the formula:

$ A_v = \beta \cdot \frac{R_L}{R_i} $

Substituting the given values into the formula:

$ \begin{aligned} A_v &= \frac{40 \times 10 \times 10^3}{2 \times 10^3} \\ A_v &= 40 \times 5 \\ A_v &= 200 \end{aligned} $

Thus, the voltage gain is 200.

Given:

Voltage gain, $ A_V = 150 $

Current gain, $ A_i = 50 $

Base resistance, $ R_B = 850 \, \Omega $

To find the resistance in the collector circuit, use the relationship for voltage gain in a common emitter transistor configuration:

$ A_V = A_i \cdot \frac{R_C}{R_B} $

Rearrange to solve for $ R_C $:

$ R_C = \frac{A_V}{A_i} \times R_B $

Substitute the given values:

$ R_C = \frac{150}{50} \times 850 $

$ R_C = 3 \times 850 $

$ R_C = 2550 \, \Omega $

Thus, the resistance in the collector circuit is $ 2550 \, \Omega $.

Let's analyze the energy gap ($E_g$) values typically associated with different materials:

Conductors (Metals):

Metals have overlapping conduction and valence bands, meaning they don’t exhibit a significant band gap.

Semiconductors:

Semiconductors usually have a moderate energy gap, commonly less than about 3 eV. For example, silicon has an energy gap of around 1.1 eV.

Both $n$-type and $p$-type semiconductors are doped forms of intrinsic semiconductors and share similar energy gap values with the pure material.

Insulators:

Insulators typically have a large energy gap, often greater than 3 eV. A 5.4 eV energy gap is well within the range for insulators.

Since the given energy gap is $5.4 \text{ eV}$, the substance falls into the insulator category.

Thus, the correct answer is:

Option A: insulator.

A p-n junction diode is utilized as a rectifier. This is because the diode allows current to flow in only one direction when it is forward-biased and prevents current flow when it is reverse-biased. This unidirectional conduction property makes the diode suitable for converting alternating current (AC) to direct current (DC), which is the primary function of a rectifier.

The answer is Option B: CE - configuration.

Here's why:

In a common emitter (CE) amplifier, the output is taken from the collector while the input is applied to the base.

The CE configuration is known for inverting the input signal, which results in a phase shift of $180^\circ$.

Other configurations like common base (CB) and common collector (CC) do not exhibit this 180° phase inversion.

Thus, when you observe that the output signal is phase-shifted by $180^\circ$, it indicates that the transistor is set up in a common emitter configuration.

For an intrinsic (pure) semiconductor, where the number of electrons is equal to the number of holes ( $n_e=n_h$ ), the intrinsic carrier concentration ( $n_i$ ) in thermal equilibrium is given by,

$ n_i^2=n_e \times n_h \Rightarrow n_i=\sqrt{n_e \times n_h} $

Given, input, $A=1$

$ \begin{aligned} & B=1 \\ & C=1 \end{aligned} $

Here, $B$ and $C$ are inputs for NAND gate.

So, output

$ \begin{aligned} & Y_1=\overline{B \cdot C} \\ & Y_1=\overline{1 \cdot 1} \Rightarrow Y_1=0 \end{aligned} $

Now, $\bar{A}$ and $Y_1$ are inputs for NOR gate.

So, output,

$ \begin{aligned} & Y_2=\overline{\bar{A}+Y_1} \\ & Y_2=\overline{0+0} \Rightarrow Y_2=1 \end{aligned} $

Therefore, $Y_1=0, Y_2=1$

When an $n$-type semiconductor is heated, thermal energy generates additional electron–hole pairs.

• Each time an electron–hole pair is generated, one electron and one hole are produced.

• So, the increase in the number of electrons and holes due to heating is equal.

Hence, on heating an $n$-type semiconductor, the number of holes and electrons increases equally.

Correct option: D

For AND gate $D_1$ out put will be $=X \cdot \bar{Y}$

For AND gate $D_2=\bar{X} \cdot Y$

For AND gate $D_3=D_1 \cdot D_2$

$ =(X \cdot \bar{Y})(\bar{X} \cdot Y)=0 $

Now writing truth table

$ \begin{array}{ccc} \hline \boldsymbol{A} & \boldsymbol{B} & \boldsymbol{Y} \\ \hline 0 & 0 & 0 \\ \hline 1 & 0 & 0 \\ \hline 0 & 1 & 0 \\ \hline 1 & 1 & 0 \\ \hline \end{array} $

Hence, option (a) is correct.

Photo-diode is a device which is reverse biased and produced current when light falls on it.

When photo-diode is reverse biased, the width of depletion layer increases and a small reverse current flows through diode.

When light falls on junction, electron-holes pair are generated in big number and these charge carriers can

easily cross the barrier. Due to reverse bias, and broad depletion layer photocurrent is significant in reverse bias even for fractional change in minority carriers.

So, option (c) is the correct option.

LED-Light emitting diode.

It is connected in forward biased. The band width of light is $10-50 \mathrm{~nm}$. No warm up time is required for LED to start.

It require very low voltage to operate. It can switch ON and OFF very quickly because very low energy required for excitation and rapidly releases this energy.

So, option (d) is correct option.

From the given logic circuit diagram

$ \begin{aligned} & & P & =\bar{X}+Y=X \cdot \bar{Y} \\ & & Q & =\overline{X \bar{Y}}=\bar{X}+\bar{Y} \\ \Rightarrow & & Q & =\bar{X}+Y \\ \text { and } & & R & =\overline{P+Q} \end{aligned} $

Where, $X=1$ and $Y=1$, then

$ \begin{aligned} & P=1 \cdot \overline{1}=1 \cdot 0=0 \\ & Q=\bar{X}+Y=\overline{1}+1=0+1=1 \\ & and\,\,\,R=\overline{P+Q}=\overline{0+1}=\overline{1}=0 \end{aligned} $

The given symbol represents $n-p-n$ transistor.

In common emitter amplifier, output voltage is $180^{\circ}$ out of phase of input voltage.

$ \begin{aligned} &\text { Effective barrier height }\\ &\begin{aligned} & =\text { barrier potential - applied voltage } \\ & =0.7 \mathrm{~V}-0.3 \mathrm{~V} \\ & =0.4 \mathrm{~V} \end{aligned} \end{aligned} $

The ratio of electron to hole current is:

$ \frac{I_e}{I_h} = \frac{7}{4} $

The ratio of the drift velocities of electrons to holes is:

$ \frac{v_{de}}{v_{dh}} = \frac{5}{4} $

In semiconductors, the drift current ($ I $) is proportional to the product of the charge carrier concentration ($ n $) and the drift velocity ($ v_d $). This relationship is expressed as:

$ I \propto n \cdot v_d $

Thus, for electron and hole currents, we can write:

$ I_e \propto n_e \cdot v_{de} $

$ I_h \propto n_h \cdot v_{dh} $

By dividing the expression for electron current by the expression for hole current, we get:

$ \frac{I_e}{I_h} = \frac{n_e \cdot v_{de}}{n_h \cdot v_{dh}} $

Substituting in the given ratios:

$ \frac{n_e}{n_h} = \frac{I_e \cdot v_{dh}}{I_h \cdot v_{de}} $

$ \frac{n_e}{n_h} = \frac{7}{4} \cdot \frac{4}{5} = \frac{7}{5} $

Thus, the ratio of the concentration of electrons to holes is $ \frac{7}{5} $ or $ 7:5 $.

Intrinstic semiconductor are those material where the charge carrier (holes and electrons) are in equal number.

Donor impurity will provide its excess electron to other atom of crystal structure.

Hence, when a semiconductor is doped with a donor impurities, it will increase the concentration of electron and at the same time decreases the holes. Concentration by favouring electron-holes pairing.

In a transistor, the currents are related by specific equations. Here's how to determine the collector current when the base and emitter currents are known:

Base current ($I_b$): $10 \, \mu \mathrm{A}$

Emitter current ($I_e$): $1 \, \mathrm{mA}$ = $1000 \, \mu \mathrm{A}$

In a transistor, the relationship between the currents is defined by the equation:

$ I_e = I_c + I_b $

Where $ I_c $ is the collector current. To find the value of $ I_c $, rearrange the equation:

$ I_c = I_e - I_b $

Substitute the given values:

$ \begin{aligned} I_c &= 1000 \, \mu \mathrm{A} - 10 \, \mu \mathrm{A} \\ &= 990 \, \mu \mathrm{A} \end{aligned} $

Thus, the collector current is $990 \, \mu \mathrm{A}$.

Output of NAND gate = Input of NOT gate

So, the output will be an AND gate.

Given, band gap in semiconductor material,

The given logic circuit diagram is shown as

Output of above logic gate is given as

$ \begin{array}{rlr} Y & =\overline{\bar{A} \cdot \bar{B}} & \text { [By de Morgan's law } \\ & =\overline{\bar{A}}+\overline{\bar{B}} & \overline{x \cdot y}=\bar{x}+\bar{y} \\ & =A+B & \because \overline{\bar{x}}=x] \\ & =\text { Output of OR gate } & \end{array} $

$ \begin{aligned} &\text { Band gap, }\\ &\begin{aligned} & E_g=2.8 \mathrm{eV} \\ &=2.8 \times 1.6 \times 10^{-19} \mathrm{~J} \\ & \Rightarrow \quad \frac{h c}{\lambda}=2.8 \times 1.6 \times 10^{-19} \\ &\,\,\,\,\,\,\, \,\,\,\,\,\,\, \,\,\,\,\,\,\, \,\,\,\,\,\,\, \,\,\,\,\,\,\, \,\,\,\,\,\,\, \,\,\,\,\,\,\, \,\,\,\,\,\,\, \quad\left[\because E_g=\frac{h c}{\lambda}\right] \\ & \Rightarrow \frac{6 \times 10^{-34} \times 3 \times 10^8}{\lambda}=2.8 \times 1.6 \times 10^{-19} \end{aligned} \end{aligned} $

$ \begin{aligned} & \Rightarrow \quad \frac{1.8 \times 10^{-25}}{\lambda}=4.48 \times 10^{-19} \\ & \Rightarrow \quad \lambda=\frac{1.8 \times 10^{-25}}{4.48 \times 10^{-19}} \\ & \quad=0.4018 \times 10^{-6} \mathrm{~m} \\ & \quad=401.8 \times 10^{-9} \mathrm{~m} \\ & \quad=401.8 \mathrm{~nm} \end{aligned} $

Hence, approximate wavelength which can detect by $p-n$ junction is less than 401.8 nm .

Therefore, wavelength of 600 nm cannot be detected by $p-n$ junction.

The given logic circuit is represented as

The output of logic gate is

$ Y=\overline{\bar{A}+\bar{B}}=\overline{\bar{A}} \cdot \overline{\bar{B}}=A \cdot B $

[By de Morgan's law, $\overline{x+y}=\bar{x} \cdot \bar{y}$ ]

= Output of AND gate

Given, number of silicon atom,

$ n_{\mathrm{Si}}=5 \times 10^{28} \text { atoms } / \mathrm{m}^3 $

Number of arsenic atom,

$ \begin{aligned} n_{\mathrm{As}} & =4.5 \times 10^{21} \text { atom } / \mathrm{m}^3 \\ n_i & =1.5 \times 10^{16} / \mathrm{m}^3 \end{aligned} $

Number of free electrons obtained from

$ \begin{aligned} \text { doping } & =n_e \\ & =n_{\mathrm{As}} \\ & =4.5 \times 10^{21} \text { electrons } / \mathrm{m}^3 \end{aligned} $

∴ Total number of electrons after doping,

$ \begin{aligned} N & =n_e+n_i \\ & =4.5 \times 10^{21}+1.5 \times 10^{16} \\ & =1.5 \times 10^{16}\left(3 \times 10^5+1\right] \\ & =1.5 \times 10^{16}\left(3 \times 10^5\right) \\ & =4.5 \times 10^{21} \end{aligned} $

$ \begin{aligned} &\text { According to mass-action law, }\\ &\begin{aligned} n_e \cdot m_h & =n_i^2 \\ n_h & =\frac{n_i^2}{n_e} \\ & =\frac{\left(1.5 \times 10^{16}\right)^2}{4.5 \times 10^{21}} \\ & =\frac{225 \times 10^{32}}{4.5 \times 10^{21}} \\ \Rightarrow \quad n_h & =5 \times 10^{10} \mathrm{holes} / \mathrm{m}^3 \\ \therefore \quad \frac{n_e}{n_h} & =\frac{4.5 \times 10^{21}}{5 \times 10^{10}} \\ & =0.9 \times 10^{11} \\ & =9 \times 10^{10} \end{aligned} \end{aligned} $

The given logic circuit diagram is

Output of the given logic gate is

$ \begin{aligned} Y & =\overline{A B} \\ & =\text { Output of NAND gate } \end{aligned} $

Dynamic resistance, $r_d=d V / d I$

Now, $I=I_0\left(e^{V / 2 V_T}-1\right)$

$ \begin{aligned} & \Rightarrow \frac{d I}{d V}=I_0\left(e^{V / 2 V_T} \cdot \frac{1}{2 V_T}\right) \\ & \Rightarrow \frac{d V}{d I}=\frac{2 V_T}{I_0} \cdot e^{\frac{V}{2 V_T}} \Rightarrow r_d=\frac{2 V_T}{I_0 \cdot e^{V / 2 V_T}} \end{aligned} $

Now, when $I=1000 I_0$, from Eq. (i) we get

$ \begin{aligned} & & I_0 \cdot 1000 & =I_0\left(e^{\frac{V}{2 V_T}}-1\right) \\ \Rightarrow & & e^{\frac{V}{2 V_T}} & =1001 \end{aligned} $

And at $I=10 I_0$,

$ e^{\frac{V}{2 V_T}}=11 $

Now, $r_d$ at $I=1000 I_0$

$ =\frac{2 V_T}{I_0} \times \frac{1}{1001} $

And $r_d$ at $I=10 I_0=\frac{2 V_T}{I_0} \times \frac{1}{11}$

Given, $r_d\left(I=1000 I_0\right)$

$ \begin{array}{rlrl} & =\alpha \cdot r_d\left(I=10 I_0\right) \\ \Rightarrow & \frac{2 V_T}{I_0} \times \frac{1}{1001} =\alpha \cdot \frac{2 V_T}{I_0} \times \frac{1}{11} \\ \Rightarrow & \alpha=\frac{11}{1001}=\frac{1}{91} \approx \frac{1}{100} \end{array} $

In a $n-p-n$ transistor, emitter region is highly doped, collector region is moderately doped and base region is lightly doped.

The given logic circuit diagram is drawn as,

The output of logic circuit is given as,

$ \begin{aligned} X & =A B+(A+B)=A B+A+B \\ & =A(B+1)+B \\ & =A \cdot 1+B\,\,\,\,\,\,\,\,\,\,\, [\because B+1=1]\\ & =A+B \\ & =\text { output of OR gate. } \end{aligned} $

When trivalent impurities ( $\mathrm{Al}, \mathrm{Ga}$, B etc.) are doped in a pure semiconductor material ( Ge or Si ), then $p$-type semiconductor is formed. In $p$-type semiconductor holes are majority charge carriers and electrons are minority charge carriers.

The truth table of NAND gate is given as

$ \begin{array}{cccc} \hline \boldsymbol{A} & \boldsymbol{B} & \boldsymbol{A} \boldsymbol{B} & \boldsymbol{Y}=\overline{\boldsymbol{A} \boldsymbol{B}} \\ \hline 0 & 0 & 0 & 1 \\ \hline 0 & 1 & 0 & 1 \\ \hline 1 & 0 & 0 & 1 \\ \hline 1 & 1 & 1 & 0 \\ \hline \end{array} $

∴ Hence, it is clear from truth table, when $A=1, B=1 ; Y=0$

At 0K , semiconductor behaves as an insulator, hence, there is no free electrons in the semiconductor at 0 K .

At room temperature or above room temperature, some covalent bonds are broken, hence some free electrons are found at these temperatures. On increasing temperature, more number of covalent bonds are broken, hence number of free electrons increases with increase of temperature of semiconductor. Conductivity of semiconductor is less than that in conductor, hence number of free electrons in semiconductor is less than that of conductor. Therefore, statements (A), (C), (D) are correct but (B) is false.

The given logic circuit diagram is shown as:

Output of the logic circuit is given as

$\begin{aligned} Y & =(\bar{A}+B)(\bar{A}+\bar{B})(A+\bar{B}) \\ & =(\bar{A} \bar{A}+\bar{A} \bar{B}+B \bar{A}+B \bar{B})(A+\bar{B}) \quad(\because B \bar{B}=0) \\ & =(\bar{A}+\bar{A} \bar{B}+B \bar{A}+0)(A+\bar{B}) \end{aligned}$

$\begin{aligned} &\begin{aligned} & =[\bar{A}(1+\bar{B})+B \bar{A}](A+\bar{B}) \\ & =(\bar{A}+B \bar{A})(A+\bar{B}) \quad (\because 1+\bar{B}=1)\\ & =\bar{A}(1+B)(A+\bar{B}) \\ & =\bar{A} \cdot 1(A+\bar{B}) \quad (\because 1+B=1)\\ & =\bar{A} A+\bar{A} \bar{B} \\ & =0+\bar{A} \bar{B} \\ & =\bar{A} \bar{B} \end{aligned}\\ \end{aligned}$

The current can be written as $ I = I_0 \sin \omega t $, where $ I_0 $ is the highest value (peak current), and $ \omega $ is the angular frequency.

To find the average value of the current ($ I_{\text{av}} $), we need to find the average over half the cycle (because the current repeats every half cycle):

$ I_{\text{av}} = \frac{1}{T/2} \int_0^{T/2} I\, dt $ where $ T $ is the time for one full cycle.

Plug in the current equation:

$ I_{\text{av}} = \frac{2}{T} \int_0^{T/2} I_0 \sin \omega t\, dt $

Take out constants and solve the integral:

$ I_{\text{av}} = \frac{2 I_0}{T} \left[ \frac{-\cos \omega t}{\omega} \right]_0^{T/2} $

Put in the values for $ t = 0 $ and $ t = T/2 $:

$ I_{\text{av}} = \frac{2 I_0}{T \omega} \left( -\cos(\omega \frac{T}{2}) + \cos(0) \right) $

Since $ \omega = \frac{2\pi}{T} $, then $ \omega \frac{T}{2} = \pi $:

$ I_{\text{av}} = \frac{2 I_0}{T \omega} [ -\cos(\pi) + \cos(0) ] $

We know $ \cos(\pi) = -1 $ and $ \cos(0) = 1 $:

$ I_{\text{av}} = \frac{2 I_0}{T \omega} [ -(-1) + 1 ] = \frac{2 I_0}{T \omega} [ 1 + 1 ] = \frac{2 I_0}{T \omega} \times 2 $

Now replace $ \omega $ with $ 2\pi / T $:

$ I_{\text{av}} = \frac{2 I_0}{T \times \frac{2\pi}{T}} \times 2 = \frac{2 I_0}{2\pi} \times 2 = \frac{2 I_0}{\pi} $

So, the average current is: $ I_{\text{av}} = \frac{2 I_0}{\pi} $

Given, change in base emitter voltage,

$\Delta V_{B E}=0.04 \mathrm{~V}$

Change in base current, $\Delta I_B=20 \mu \mathrm{A}$

Change in collector current, $\Delta I_C=2 \mathrm{~mA}$

$\because$ Input resistance,

$\begin{aligned} R_{\text {in }} & =\frac{\Delta V_{B E}}{\Delta I_B} \\ & =\frac{0.04}{20 \times 10^{-6}}=2 \times 10^3 \Omega \\ & =2 \mathrm{k} \Omega \end{aligned}$

$\text { current gain, } \begin{aligned} \beta & =\frac{\Delta I_C}{\Delta I_B} \\ & =\frac{2 \times 10^{-3}}{20 \times 10^{-6}}=10^2=100 \end{aligned}$

Given,

Here, X = A + B

$\therefore$ It is an output of OR gate.

Given, collector voltage, $V_c=8V$

Voltage drop across resistor, $R=800\Omega$

and $V=0.5$ V

Current gain, $\alpha=0.96$

Let, collector, emitter and base current be $I_C, I_E$ and $I_B$, respectively.

Since, $\alpha=\frac{I_C}{I_E}$

and $I_E =I_B+I_C$

$\because \alpha =\frac{I_C}{I_B+I_C}=\frac{1}{\frac{I_B}{I_C}+1}$

$\Rightarrow \frac{I_B}{I_C} =\frac{1}{\alpha}-1$

$=\frac{100}{96}-1=\frac{4}{96}=0.042$

$\begin{aligned} \Rightarrow \quad I_B & =0.042 I_C=0.042 \times \frac{0.5}{800}\left(\because I_C=\frac{V}{R}\right) \\ & =\frac{42 \times 10^{-3} \times 5 \times 10^{-1}}{800} \\ & =2.625 \times 10^{-5} \mathrm{~A} \end{aligned}$

In $p-n-p$ transistor the collector current is slightly less than emitter current because the emitter-base junction is forward biased, so the majority charge carries (holes) of

emitter get replaced from the positive terminal and move towards base. As, base is lightly dopped, some of the holes combine with the majority charge carries electrons present in the base and most of the holes reach the collector, crossing the collector-base junction. So, current in the circuit is $I_E=I_B+I_C$

The Boolean expression of NOR gate is

$ Y=\overline{A+B} $

where, $A$ and $B$ are inputs and $Y$ is the output.

Truth table of NOR gate is

$ \begin{array}{ccc} \hline \boldsymbol{A} & \boldsymbol{B} & \boldsymbol{Y}=\overline{\boldsymbol{A}+\boldsymbol{B}} \\ \hline 0 & 0 & 1 \\ \hline 0 & 1 & 0 \\ \hline 1 & 0 & 0 \\ \hline 1 & 1 & 0 \\ \hline \end{array} $

Hence, when all inputs ( $A$ and $B$ ) are low ( 0 ), then output of NOR gate is high (1).

$ \text { In option (a) } $

where, $D=A \cdot \bar{B}+\bar{A} \cdot B$

Put $A=1$ and $B=1$,

then $D=1 \cdot \overline{1}+\overline{1} \cdot 1=1 \cdot 0+0 \cdot 1=0+0=0$

So, this option is wrong.

In option (b)

$ \begin{aligned}where,\,\, D & =[\overline{[(\bar{A}+B)+(A+\bar{B}]} \\ & =[\overline{(\bar{A}+A)+(B+\bar{B})}] \end{aligned} $

$ \begin{aligned} & \text { } \begin{aligned}Put\,\, A & =1 \text { and } B=1, \\ \text { then } D & =[(\overline{1+1}+(1+\overline{1}) \\ & =[\overline{(0+1)+(1+\overline{0})}]=\overline{[1+1]}=\overline{[1]}=0 \end{aligned} \end{aligned} $

So, this option is wrong.

In option (c)

where, $D=(A+B) \cdot(\bar{A}+\bar{B})$

$ \begin{aligned} & =A \cdot \bar{A}+A \cdot \bar{B}+B \cdot \bar{A}+B \cdot \bar{B} \\ & =0+A \cdot \bar{B}+B \cdot \bar{A}+0=A \cdot \bar{B}+\bar{A} \cdot B \end{aligned} $

Put $A=1$ and $B=1$,

$ \text { } \begin{aligned} then\,\, D & =1 \cdot \overline{1}+\overline{1} \cdot 1 \\ & =1 \cdot 0+0 \cdot 1=0+0=0 \end{aligned} $

So, this option is wrong.

In option (d)

where, $D=A \cdot B+\bar{A} \cdot \bar{B}$

Put $A=1$ and $B=1$,

Given, base current in $n-p-n$ transistor,

$ I_B=2 \mathrm{~mA}=2 \times 10^{-3} \mathrm{~A} $

Since, $95 \%$ of emitted electrons reach the collector, hence Collector current,

$ \begin{equation*} I_C=95 \% \text { of } I_E \Rightarrow I_C=0.95 I_E \Rightarrow I_E=\frac{I_C}{0.95} \,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,...(i) \end{equation*} $

But we know that, $I_E=I_C+I_B$

$ \Rightarrow \quad \frac{I_C}{0.95}=I_C+2 \times 10^{-3} \Rightarrow \frac{I_C}{0.95}-I_C=2 \times 10^{-3} $

The circuit given is as shown

Potential drop across

$ R_L=V_L=V_Z=10 \mathrm{~V} $

Potential drop across $4 \mathrm{k} \Omega$ resistance is

$ V_R=60-10=50 \mathrm{~V} $

Current through $4 \mathrm{k} \Omega$ resistance is

$ I=\frac{V_R}{R}=\frac{50}{4 \times 10^3}=12.5 \times 10^{-3} $

$\mathrm{A}=12.5 \mathrm{~mA}$

Current through load resistance $=I_L$

$ =\frac{V_L}{R_L}=\frac{10}{2 \times 10^3}=5 \mathrm{~mA} $

Also, $I_Z=I-I_L=12.5-5=7.5 \mathrm{~mA}$

Phosphorous is a pentavalent impurity.

So, resulting semiconductor is a $n$-type semiconductor. The energy band diagram of a $n$-type semiconductor is shown below

So, the energy levels of impurity atom created in the semiconductor are close to the bottom of the conduction band.

The output of full wave rectifier with capacitor filter for the given AC input is given as

The given logic circuit is

∴ Boolean expression of the given logic circuit is given as

$ Y=\bar{A}+B $