Semiconductor Electronics

For ideal diode, forward resistance $=0$ and reverse biased resistance $=\infty$

$\therefore \quad$ Circuit can be redrawn as,

$ \begin{aligned} I & =\frac{10}{2}+\frac{10}{4} \\ & =\frac{30}{4}=\frac{15}{2} \mathrm{~A} \end{aligned} $

Voltage drop will be across the diode, when it will be in reverse bias 1

In positive half cycle it will be in reverse biased

$V-I$ characteristics of a forward-biased junction diode

When forward bias voltage increases beyond threshold voltage, diode current increases significantly. This is not reverse saturation current.

To determine the state of the diodes in the full wave rectifier circuit at $ t = 15 \, \text{ms} $, we analyze the input supply voltage given by:

$ V_{\text{in}} = 220 \sin(100 \pi t) $

Here are the key steps to explain the situation:

Substitute the Time: Convert $ t = 15 \, \text{ms} $ to seconds:

$ t = 0.015 \, \text{s} $

Calculate the Angular Frequency:

$ \omega = 100\pi $

Determine the Period:

$ \frac{2\pi}{T} = 100\pi \quad \Rightarrow \quad T = \frac{1}{50} \, \text{s} = 0.02 \, \text{s} $

Calculate the Phase:

$ t = \frac{3T}{4} $

This corresponds to the negative half-cycle of the sine wave, occurring when the input voltage goes negative.

Given the circuit configuration during the negative half-cycle:

$ D_1 $ is reverse biased.

$ D_2 $ is forward biased.

Hence, at $ t = 15 \, \text{ms} $, the diode $ D_1 $ is reverse biased, and diode $ D_2 $ is forward biased, allowing current to flow through diode $ D_2 $.

$\begin{aligned} & Y_1=\overline{A+B} \\ & Y_2=\overline{A \cdot B} \\ & Y=Y_1 \cdot Y_2 \\ & =\overline{A+B} \cdot \overline{A \cdot B} \\ & =\overline{(A+B)+A \cdot B} \\ & =\overline{A+B(1+A)} \\ & =\overline{A+B} \text { NOR gate } \end{aligned}$

The I-V characteristics of solar cell is

When the output of an OR gate is applied as input to a NOT gate, the combination acts as a NOR gate. To understand why, let's examine the behavior of these logic gates.

An OR gate outputs a logic high (1) when at least one of its inputs is high. Mathematically, this can be expressed as:

$ Y_{\text{OR}} = A + B $

Where $ A $ and $ B $ are the inputs, and $ Y_{\text{OR}} $ is the output of the OR gate.

An OR gate followed by a NOT gate inverts this output. The NOT gate, also known as an inverter, changes a high input to a low output, and vice versa. So the output of the NOT gate can be expressed as:

$ Y_{\text{NOT}} = \overline{Y_{\text{OR}}} = \overline{(A + B)} $

This is exactly the logic operation performed by a NOR gate. Therefore, this combination of an OR gate followed by a NOT gate behaves as a NOR gate.

So, the correct answer is Option B: NOR gate.

$Y=\overline{\bar{A} \bar{B}}=A+B$

According to given truth table, output is independent on value of $A$

$\therefore$ Output $Y=\bar{B}$

A : Solar cell characteristics

B : In reverse biased $p n$ junction diode, the current measured in $(\mu \mathrm{A})$, is due to minority charge carrier.

$ \begin{aligned} Y_1 & =\overline{A \cdot A} \\ & =\bar{A} \\ Y_2 & =\overline{B+B} \\ & =\bar{B} \\ Y & =\overline{Y_1+Y_2} \\ & =\overline{\bar{A}+\bar{B}} \\ & =\overline{\bar{A}} \cdot \overline{\bar{B}} \end{aligned} $

= A.B is similar to output of AND gate.

Electrical conductivity is a measure of a material's ability to conduct an electric current. The higher the conductivity, the lower the resistivity. So, if we are looking for the material with the smallest resistivity, we are looking for the material with the highest electrical conductivity.

Among the options given, silver (Option B) is known to have the highest electrical conductivity and thus, the smallest resistivity. Germanium (Option A) and silicon (Option D) are semiconductors, meaning they have moderate conductivity that can be manipulated, while glass (Option C) is generally a poor conductor, or an insulator. Therefore, silver is the correct answer.

$Y = \overline {\overline A + \overline B } = \overline{\overline A} \,.\,\overline{\overline B} = A\,.\,B$

AND gate

for AND gate

For p type semiconductor trivalent impurity added

In given symbol, emitter current leave from emitter so transistor is NPN

order of doping $\mathrm{E}>\mathrm{C}>>\mathrm{B}$

order of size $\mathrm{C}>\mathrm{E}>>\mathrm{B}$

for active mode emitter base junction is forward bias and base-collector junction is reverse bias.

Statement I : Photocell/solar cell convert light energy into electric energy/current.

Statement II : We use zener diode in reverse biased condition, when reverse biased voltage more than break down voltage than it act as stablizer.

Capacitor used to remove AC ripples from Rectifier output.

$y=\overline{\overline{\mathrm{A}} \cdot \overline{\mathrm{B}}}=\overline{\overline{\mathrm{A}}}+\overline{\overline{\mathrm{B}}}$

$=(\mathrm{A}+\mathrm{B}) ~\mathrm{OR}$ Gate

The given circuit clearly indicates that the bulb will glow when either of the switches are closed.

The corresponding truth table will be

This suggests that it will correspond to OR gate.

Zener diode is special purpose p-n junction diode, which is generally operated in reverse bias for its operation of voltage regulation. It is a heavily doped p-n junction. Due to large doping concentration depletion width is narrower.

Given ${I_C} = 24$ mA

$\alpha = 0.8 = {{{I_C}} \over {{I_E}}}$

${I_E} = {{24} \over {0.8}}$ mA $ = 30$ mA

${I_B} = {I_E} - {I_C} = 30 - 24$

$ = 6$ mA, entering the base

Potential drops across the p-n junctions will be same if either both junctions are forward biased or both junction are reverse biased.

In figure (a) and (c), both junctions are forward biased therefore both have same potential.

In figure (b) first junction is forward biased and second junction is reverse biased, so both junctions have different potential difference.

As the temperature increases the resistivity of the conductor increases hence the electrical resistance increases. However for semiconductor the resistivity decreases with the temperature. Hence electrical resistance of semiconductor decreases.

In half wave rectifier, the output frequency is same as that of input frequency.

$C = \left( {\overline {A\,.\,B} } \right)\,.\,\left( {\overline {\overline A \,.\,B} } \right)$

$ \Rightarrow C = \overline {A\,.\,B + \overline A \,.\,B} $

$ \Rightarrow C = \overline {\left( {A + \overline A } \right)B} $

$ \Rightarrow C = \overline B $

The truth table would be

Given, $R_{\text {out }}=200 \Omega, R_{\text {in }}=100 \mathrm{k} \Omega=10^5 \Omega$

$V_{C C}=3 \mathrm{~V}, V_{B E}=0.7 \mathrm{~V}, V_{C E}=0 \mathrm{~V}, \beta=200$

Applying KVL at output side,

$\begin{aligned} & & V_{C E} & =V_{C C}-I_C R_{\text {out }} \\ & & 0 & =3-I_c \times 200 \\ \Rightarrow & & I_C & =15 \mathrm{~mA} \\ \therefore & & I_\beta & =\frac{I_C}{\beta}=\frac{15 \times 10^{-3}}{200}=75 \times 10^{-6} \mathrm{~A} \\ \therefore & & I_B & =75 \mu \mathrm{A} \end{aligned}$

Again, Applying KVL at input side,

$\begin{aligned} V_{B E} & =V_{B B}-I_B R_{\text {in }} \\ \Rightarrow \quad V_{B B} & =V_{B E}+I_B R_{\text {in }} \\ & =0.7+75 \times 10^{-6} \times 10^5 \\ & =0.7+7.5=8.2 \mathrm{~V} \end{aligned}$

Given, voltage across Zener diode, $V_Z=6 \mathrm{~V}$

Since, Zener diode provide statelised supply of $6 \mathrm{~V}$.

In this case, the value of $R$ should be chosen such that negligible current flows through the Zener diode.

$\begin{aligned} & \therefore \quad I=I_Z+I_L=0+I_L \\ & I=\frac{30}{R+10^3} \\ & \text { But } \quad I=6 \mathrm{~mA}=6 \times 10^{-3} \mathrm{~A} \\ & \therefore \quad 6 \times 10^{-3}=\frac{30}{R+10^3} \\ & \Rightarrow \quad R=4 \times 10^3 \Omega=4 \mathrm{~k} \Omega \\ & \end{aligned}$

A p-n junction photo diode can be operated under photovoltaic conditions similar to that of a solar cell. The current-voltage characteristics of a photodiode under illumination are also similar. When light energy falls on the solar cell, then it converts solar energy into electrical energy. The area of solar is larger so that it could absorbed more amount of sunlight and hence more amount electrical energy is obtained. Hence, assertion and reason both are true but Reason is not the correct explanation of assertion.

Current passing in the circuit is

$I=\frac{P}{V}=\frac{100 \times 10^{-3}}{0.5}=0.2 \mathrm{~A}$

Value of connected series resistance,

$\begin{aligned} & R=\frac{1.5-0.5}{0.2} \Rightarrow R=\frac{1}{0.2} \\\\ \therefore R & =5 \Omega \end{aligned}$

Thickness of depletion layer depends upon the biasing of semiconductor devices and in the depletion layer, there is no free charge carriers are available in depletion layer.

Given, $\quad \beta=49$

Current gain $\beta=\frac{\Delta I_C}{\Delta I_B}$, where $\Delta I_C$ is change in collector current and $\Delta I_B$ is change in base current.

$\begin{aligned} \Delta I_C & =\beta \Delta I_B=49 \times 5 \\ & =245 \mu \mathrm{A} \\ \Delta I_E & =\Delta I_B+\Delta I_C \\ & =(245+5) \mu \mathrm{A} \\ & =250 \mu \mathrm{A} \end{aligned}$

Given for one indium atom to be doped in $5 \times 10^7$ silicon atoms.

Number density of silicon $=5 \times 10^{22}$

Number of acceptor atom$/ \mathrm{cm}^3=\frac{5 \times 10^{22}}{5 \times 10^7}$

$=1 \times 10^{15} \mathrm{~cm}^{-3}$

Hence, number of acceptor atom$/ \mathrm{cm}^3$ is $1 \times 10^{15} \mathrm{~cm}^{-3}$.

The simplified circuit is shown in figure below.

So, output $y=\overline{\bar{A} \cdot \bar{B} \cdot \bar{C}}$

If $\quad A=0, B=1, C=1$

$\therefore \quad y=\overline{\overline{0} \cdot \overline{1} \cdot \overline{1}}=\overline{1 \cdot 0 \cdot 0}=\overline{0}=1$