Semiconductor

For the input voltages at A and B we assume a positive logic system where 0 V represents logic 0 (LOW) and 5 V represents logic 1 (HIGH).

The supply voltage $\mathrm{V}_{\mathrm{dc}}=5 \mathrm{~V}$ connected through a resistor R to the output C .

Diodes $\mathrm{D}_1$ and $\mathrm{D}_2$ are connected with their n -sides (cathodes) toward the inputs A and B . They act as switches.

$ \mathrm{A}=0 \mathrm{~V}, \mathrm{~B}=0 \mathrm{~V} \text { (Both LOW) } $

Both diodes are forward-biased because the p -side (connected to $\mathrm{V}_{\mathrm{dc}}$ ) is at a higher potential than the n -side (connected to 0 V ). Current flows through the diodes to the ground. This pulls the potential at C down to approximately 0 V , i.e., output $\mathrm{C}=0$ (LOW).

$ \begin{array}{|l|l|l|} \hline \text { A } & \text { B } & \text { C } \\ \hline 0 & 0 & 0 \\ \hline \end{array} $

$\mathrm{A}=0 \mathrm{~V}, \mathrm{~B}=5 \mathrm{~V}$ (One LOW, One HIGH)

Diode $\mathrm{D}_1$ is forward-biased and conducts current to the 0 V input. This shorts point C to ground through the conducting diode. Diode $\mathrm{D}_2$ is reverse-biased and does not conduct. Because $\mathrm{D}_1$ is conducting, point C remains at approximately 0 V , i.e., output $\mathrm{C}=0$ (LOW).

$ \begin{array}{|l|l|l|} \hline \text { A } & \text { B } & \text { C } \\ \hline 0 & 1 & 0 \\ \hline \end{array} $

$ \mathrm{A}=5 \mathrm{~V}, \mathrm{~B}=0 \mathrm{~V} \text { (One HIGH, One LOW) } $

Diode $\mathrm{D}_2$ is forward-biased and conducts current to the 0 V input at B . This pulls point C down to ground level, i.e., output $\mathrm{C}=0$ (LOW).

$ \begin{array}{|l|l|l|} \hline \text { A } & \text { B } & \text { C } \\ \hline 1 & 0 & 0 \\ \hline \end{array} $

$ \mathrm{A}=5 \mathrm{~V}, \mathrm{~B}=5 \mathrm{~V} \text { (Both HIGH) } $

Both n -sides and p -sides of the diodes are at 5 V (or the n -side is higher than the p -side). The diodes do not conduct, i.e., they are OFF. Since no current flows through the resistor R, there is no voltage drop across it. Therefore, point C stays at the supply voltage of 5 V , i.e., output $\mathrm{C}=1(\mathrm{HIGH})$.

$ \begin{array}{|l|l|l|} \hline \text { A } & \text { B } & \text { C } \\ \hline 1 & 1 & 1 \\ \hline \end{array} $

The resulting truth table for the given circuit is,

$ \begin{array}{|l|l|l|} \hline A & B & C \\ \hline 0 & 0 & 0 \\ \hline 0 & 1 & 0 \\ \hline 1 & 0 & 0 \\ \hline 1 & 1 & 1 \\ \hline \end{array} $

Hence, the logic gate is an AND Gate, where the output is HIGH only when all inputs are HIGH.

Hence, the correct option is (A).

For diodes $\mathrm{D}_1$ and $\mathrm{D}_3$, the p -side (anode) of these diodes is connected toward the positive terminal of the 12 V source. Therefore, $D_1$ and $D_3$ are forward biased.

In diode $D_2$ the $n$-side (cathode) of this diode is connected toward the positive terminal. Therefore, $D_2$ is reverse biased and acts as an open circuit (no current flows through it).

Since $\mathrm{D}_1$ and $\mathrm{D}_3$ are in forward bias and are silicon diodes, the voltage drop across them is fixed at $\mathrm{V}_{\mathrm{d}}=0.7 \mathrm{~V}$. Because they are in parallel, the voltage at the junction after resistor $R_1$ is 0.7 V relative to the ground.

The total current flows through the resistor $\mathrm{R}_1=0.3 \mathrm{k} \Omega$. Using Ohm's Law :

$\Rightarrow $ $ V_{R 1}=V_{\text {source }}-V_d $

$ \mathrm{V}_{\mathrm{R} 1}=12 \mathrm{~V}-0.7 \mathrm{~V}=11.3 \mathrm{~V} $

So, the total current is,

$ \mathrm{i}_{\text {total }}=\frac{\mathrm{V}_{\mathrm{R} 1}}{\mathrm{R}_1}=\frac{11.3}{0.3 \mathrm{k} \Omega} $

$\Rightarrow $ $ \mathrm{i}_{\text {total }} \approx 37.7 \mathrm{~mA} $

The total current $I_{\text {total }}$ reaches the parallel junction and splits between the two forward-biased diodes, $D_1$ and $\mathrm{D}_3$. Since the diodes are identical, the current splits equally:

$ \mathrm{i}_{\mathrm{D} 1}=\frac{\mathrm{I}_{\mathrm{total}}}{2} $

$\Rightarrow $ $ \mathrm{i}_{\mathrm{D} 1}=\frac{37.7}{2} \approx 18.8 \mathrm{~mA} $

Hence, the correct option is (B).

Logic gate 1 is an AND gate with both inputs shorted together to $A$. So, the output $\left(Y_1\right)$ is just $A$.

$ \begin{array}{|c|c|c|} \hline A & B & Y_1 \\ \hline 0 & 0 & 0 \\ \hline 0 & 1 & 0 \\ \hline 1 & 0 & 1 \\ \hline 1 & 1 & 1 \\ \hline \end{array} $

Logic Gate 2 is an NAND gate with inputs A and B and its output is $\mathrm{Y}_2$.

$ \begin{array}{|c|c|c|c|} \hline A & B & A \cdot B & Y_2=\overline{A \cdot B} \\ \hline 0 & 0 & 0 & 1 \\ \hline 0 & 1 & 0 & 1 \\ \hline 1 & 0 & 0 & 1 \\ \hline 1 & 1 & 1 & 0 \\ \hline \end{array} $

Logic gate 3 is an AND gate with both inputs shorted to the output of the logic gate 2. So, the output ( $Y_3$ ) is just the output of logic gate 2.

$ \begin{array}{|c|c|c|c|c|} \hline A & B & A \cdot B & Y_2=\overline{A \cdot B} & Y_3 \\ \hline 0 & 0 & 0 & 1 & 1 \\ \hline 0 & 1 & 0 & 1 & 1 \\ \hline 1 & 0 & 0 & 1 & 1 \\ \hline 1 & 1 & 1 & 0 & 0 \\ \hline \end{array} $

Logic gate 4 is an AND gate that takes the output from the outputs $(\mathrm{Y})$ of logic gate 1 and the logic gate 3.

$ \begin{array}{|c|c|c|c|c|} \hline A & B & Y_1 & Y_3 & Y=Y_1 \cdot Y_3 \\ \hline 0 & 0 & 0 & 1 & 0 \\ \hline 0 & 1 & 0 & 1 & 0 \\ \hline 1 & 0 & 1 & 1 & 1 \\ \hline 1 & 1 & 1 & 0 & 0 \\ \hline \end{array} $

Therefore, the truth table of the given logic gate is,

$ \begin{aligned} &\begin{array}{|c|c|c|} \hline A & B & Y \\ \hline 0 & 0 & 0 \\ \hline 0 & 1 & 0 \\ \hline 1 & 0 & 1 \\ \hline 1 & 1 & 0 \\ \hline \end{array}\\ &\text { Hence, the correct option is (A) } \end{aligned} $

The gate I is OR Gate. It receives inputs n and m . Its output is $\mathrm{Y}_1=\mathrm{n}+\mathrm{m}$.

Gate II is NAND Gate. It receives two inputs, the original input n and the output of the OR gate $\left(\mathrm{Y}_1\right)$. Its output z is the result of an AND operation followed by a NOT operation, $\mathrm{z}=\overline{\mathrm{n} \cdot(\mathrm{n}+\mathrm{m})}$.

Using Boolean algebra laws :

$ \mathrm{z}=\overline{\mathrm{n} \cdot(\mathrm{n}+\mathrm{m})} $

$\Rightarrow $ $ \mathrm{z}=\overline{(\mathrm{n} \cdot \mathrm{n})+(\mathrm{n} \cdot \mathrm{~m})} $

Since $\mathrm{n} \cdot \mathrm{n}=\mathrm{n}$, the expression simplifies to $\mathrm{z}=\overline{\mathrm{n}+(\mathrm{n} \cdot \mathrm{m})}=\overline{\mathrm{n}}$

Truth table,

The output z is purely the inverse of input n . When $\mathrm{n}=0, \mathrm{z}=1$. When $\mathrm{n}=1, \mathrm{z}=0$.

$ \begin{array}{c|c|c} n & m & z \\ \hline 0 & 0 & 1 \\ 0 & 1 & 1 \\ 1 & 1 & 0 \\ 1 & 0 & 0 \end{array} $

Therefore, the correct option is (A).

The given logic gate is,

Gate 1 is an AND gate for the inputs A and $\mathrm{B}, \Rightarrow \mathrm{Y}_1=\mathrm{A} \cdot \mathrm{B}$

Gate 2 is an OR gate for the inputs C and $\mathrm{D}, \Rightarrow \mathrm{Y}_2=\mathrm{C}+\mathrm{D}$

Gate 3 is a NOT gate for which the input is $Y_1$ (the output of gate 1), $Y_3=\overline{Y_1}$

Gate 4 is an AND gate for inputs $Y_2$ and $Y_3, Y_4=Y_3 \cdot Y_2$

Gate 5 is a NOT gate which inverts the output of Gate 4 to give the final output, $Y=\overline{\mathrm{Y}_4}$

So, the final truth table is,

Hence, the correct option is (A).

Gate 1 is a NOR gate with both inputs tied together to A. A NOR gate with shorted inputs acts as a NOT gate.

$ Y_1=\overline{A+A}=\bar{A} $

Gate 2 is also a NOR gate with both inputs tied to B , which acts as a NOT gate.

$ Y_2=\overline{B+B}=\bar{B} $

Gate 3 is a NAND gate receiving inputs $Y_1$ and $Y_2$.

$ Y_3=\overline{Y_1 \cdot Y_2} $

Gate 4 is a NOR gate receiving inputs C and D .

$ Y_4=\overline{C+D} $

For the LED to emit light, it must be forward-biased. The anode is connected to output of gate 1 and gate 2, i.e., $Y_3$. The cathode is connected to the output of gate 4 , i.e., $Y_4$.

To achieve forward bias in a digital logic circuit, the anode must be at a HIGH voltage (1) and the cathode must be at a LOW voltage (0). Therefore, the required conditions are:

$ Y_3=1 * Y_4=0 $

In case of 1101 , the anode is HIGH and the cathode is LOW. The LED is forward-biased and ON.

Therefore, the correct option is (D).

At steady state (very long time), in a DC circuit, a capacitor is fully charged and it acts as an open circuit. No current flows through the branch containing the capacitor.

The diodes are ideal which acts as a closed switch (conducting) in forward-biased state and acts as a open switch (non-conducting) in reverse-biased state.

$1 \Omega$ resistor is connected directly across the battery. So, the current flows here.

$2 \Omega$ resistor is connected directly across the battery. Current flows here before reaching steady state.

The diode $D_1$ is pointing toward the positive terminal. This means it is reverse-biased. So, no current flows through this branch.

The diode $\mathrm{D}_2$ is pointing away from the positive terminal toward the negative terminal. This means it is forward-biased. Current flows through this branch.

In the steady state, when capacitor is fully charged and acts as open circuit; the resulting circuit will be,

The voltage across the capacitor is equal to the voltage across points B and G , i.e., between A and H .

The current in the close loop ABCDEFGH ,

$ \mathrm{i}=\frac{2.5}{1+4} \mathrm{~A}=0.5 \mathrm{~A} $

So, the voltage across the capacitor is, $\mathrm{V}_{\mathrm{BG}}=\mathrm{V}_{\mathrm{AH}}=(2.5-1 \times 0.5) \mathrm{V}=2.0 \mathrm{~V}$

The formula for charge stored in a capacitor is :

$ \mathrm{Q}=\mathrm{C} \times \mathrm{V} $

The capacitance is $\mathrm{C}=5 \mu \mathrm{~F}$

$ Q=5 \mu \mathrm{~F} \times 2.0 \mathrm{~V} $

$\Rightarrow $ $ Q=10.0 \mu \mathrm{C} $

Therefore, the charge stored by the capacitor in the steady state is $10.0 \mu \mathrm{C}$.

Hence, the correct option is (C).

The circuit is composed entirely of NOR gates. A NOR gate with its inputs tied together (or receiving the same signal) acts as a NOT gate.

If input is $A$, the output is $\overline{A+A}=\bar{A}$

$ \begin{array}{|l|l|l|l|} \hline \text { Input 1 } & \text { Input 2 } & \text { OR Output } & \text { NOR Output } \\ \hline 1 & 1 & 1 & 0 \\ \hline 0 & 0 & 0 & 1 \\ \hline \end{array} $

$ \begin{array}{|l|l|l|l|l|l|} \hline \mathrm{A} & \mathrm{~B} & \mathrm{Y}_1=\overline{\mathrm{A}} & \mathrm{Y}_2=\overline{\mathrm{B}} & \mathrm{Y}_3=\overline{\mathrm{Y}_1+\mathrm{Y}_2} & \mathrm{Y}_4=\overline{\mathrm{Y}_3} \\ \hline 1 & 1 & 0 & 0 & 1 & 0 \\ \hline 1 & 0 & 0 & 1 & 0 & 1 \\ \hline 0 & 1 & 1 & 0 & 0 & 1 \\ \hline 0 & 0 & 1 & 1 & 0 & 1 \\ \hline \end{array} $

The final expression $\mathrm{Y}=\overline{\mathrm{A} \cdot \mathrm{B}}$ is the characteristic equation for a NAND gate.

Therefore, the circuit functions as a NAND gate.

Hence, the correct option is (D).

The inputs are,

Interval I: From $\mathrm{t}=0$ to $\mathrm{t}=1$, Input $\mathrm{A}=0$, Input $\mathrm{B}=1$.

Interval II: From $\mathrm{t}=1$ to $\mathrm{t}=2$, Input $\mathrm{A}=1$, Input $\mathrm{B}=1$.

Interval III: From $\mathrm{t}=2$ to $\mathrm{t}=3$, Input $\mathrm{A}=1$, Input $\mathrm{B}=0$.

For the output $Y_1$ the inputs are $A$ and $B$ directly. The corresponding logic gate is AND gate.

$ \mathrm{Y}_1=\mathrm{A} \cdot \mathrm{~B} $

$ \begin{array}{|l|l|l|l|} \hline \text { Interval } & \text { Input A } & \text { Input B } & \text { Output } \mathrm{Y}_1 \\ \hline \text { I } & 0 & 1 & 0 \cdot 1=0 \\ \hline \text { II } & 1 & 1 & 1 \cdot 1=1 \\ \hline \text { III } & 1 & 0 & 1 \cdot 0=0 \\ \hline \end{array} $

For the output $\mathrm{Y}_2$ the input B is directly but input A passes through a NOT gate .

$ Y_2=\bar{A} \cdot B $

$ \begin{array}{|l|l|l|l|l|} \hline \text { Interval } & \text { Input A } & & \bar{A} & \text { Input B } \\ \hline \text { I } & 0 & 1 & 1 & \text { Output } \mathrm{Y}_2 \\ \hline \text { II } & 1 & 0 & 1 & 0 \cdot 1=0 \\ \hline \text { III } & 1 & 0 & 0 & 0 \cdot 0=0 \\ \hline \end{array} $

For the final output Y the inputs are $\mathrm{Y}_1$ and $\mathrm{Y}_2$. The corresponding gate is OR gate.

$ Y=Y_1+Y_2 $

Based on the logic analysis of the timing intervals, the correct output graph is represented in option (B).

$Y_1$ is the output of NOT Gate which takes input $A . Y_1=\bar{A}$

$ \begin{array}{|l|l|} \hline \text { Input }(\mathrm{A}) & \text { Output }\left(\mathrm{Y}_1=\overline{\mathrm{A}}\right) \\ \hline 1 & 0 \\ \hline 0 & 1 \\ \hline \end{array} $

$Y_2$ is the output of OR Gate which takes inputs $Y_1$ and $B . Y_2=Y_1+B=\bar{A}+B$

$Y_3$ is the output of AND Gate which takes inputs $Y_1$ and $B \cdot Y_3=Y_1 \cdot B=\bar{A} \cdot B$

$Y$ is the output of NOR Gate which takes inputs $Y_2$ and $Y_3 . Y=\overline{Y_2+Y_3}$

For both input sets ( $A=1, B=1$ ) and ( $A=0, B=1$ ), the output $Y$ is 0 .

Thus, the correct option is ( $C$ ).

The input voltage is $\mathrm{V}_{\mathrm{s}}=5 \mathrm{~V}$.

The total current in shunt resistance is $\mathrm{I}_{\mathrm{s}}=0.5 \mathrm{~mA}=0.5 \times 10^{-3} \mathrm{~A}$.

The power rating of LED is $\mathrm{P}_{\mathrm{LED}}=2 \mathrm{~mW}=2 \times 10^{-3} \mathrm{~W}$.

The resistance added parallel to LED is R $=1 \mathrm{k} \Omega=1000 \Omega$.

As the diode in branch containing $R$ is in reverse biased, so current through it is zero. Hence, the current through LED is same as that through $\mathrm{R}_{\mathrm{S}}, \mathrm{I}_{\text {LED }}=0.5 \mathrm{~mA}=0.5 \times 10^{-3} \mathrm{~A}$

The power rating of LED is $2 \times 10^{-3} \mathrm{~W}$,

Since $\mathrm{V}_{\mathrm{L}}=\mathrm{I}_{\mathrm{R}} \times \mathrm{R}$, we have $\mathrm{I}_{\mathrm{R}}=\frac{\mathrm{V}_{\mathrm{L}}}{1000}$.

To find the maximum safe operating voltage for the LED, we use the power formula:

$ \mathrm{P}=\mathrm{V} \times \mathrm{I} $

The power consumed by the LED is $\mathrm{P}_{\mathrm{LED}}=\mathrm{V}_{\mathrm{L}} \times \mathrm{I}_{\mathrm{LED}}$.

$ 2 \times 10^{-3}=V_L \times 0.5 \times 10^{-3} \Rightarrow V_L=4 V $

From the circuit, the voltage drop across $R_S$ is $V_{R_S}=V_S-V_L$.

$ V_{R_S}=5 \mathrm{~V}-4 \mathrm{~V}=1 \mathrm{~V} $

By Ohm's Law $\mathrm{R}_{\mathrm{S}}=\frac{\mathrm{V}_{\mathrm{R}_{\mathrm{S}}}}{\mathrm{I}_{\mathrm{s}}}=\frac{1}{0.5 \times 10^{-3}}=2 \times 10^3 \Omega=2 \mathrm{k} \Omega$

Therefore, the minimum value of the resistance $\mathrm{R}_{\mathrm{S}}$ to ensure that LED is not damaged is $2 \mathrm{k} \Omega$. Thus, the correct option is (B).

For a $p$-$n$ junction diode, the depletion region extends more into the side which is less heavily doped.

Here,

• Doping on $p$-side:

  $N_p = 10^{15}\ \text{cm}^{-3}$

• Doping on $n$-side:

  $N_n = 10^{18}\ \text{cm}^{-3}$

Clearly,

$N_p < N_n$

So, the $p$-side is much less doped than the $n$-side.

In a depletion region, charge neutrality must be maintained, so

$N_p x_p = N_n x_n$

where

• $x_p$ = depletion width on $p$-side

• $x_n$ = depletion width on $n$-side

Thus,

$\frac{x_p}{x_n} = \frac{N_n}{N_p} = \frac{10^{18}}{10^{15}} = 10^3$

So,

$x_p = 1000\, x_n$

This means the depletion region is much wider on the $p$-side than on the $n$-side.

Therefore, the correct statement is:

$\boxed{\text{Option B}}$

The depletion region width is more on $p$-side compared to that in $n$-side.

The assertion is true.

In a reverse-biased diode, the current is very small and remains almost constant with increase in reverse voltage. This small current is called reverse saturation current. When the reverse voltage reaches a critical value called breakdown voltage, the current increases sharply.

So, Assertion A is correct.

Now consider the reason.

In reverse bias, the current below breakdown is due to minority charge carriers, not majority charge carriers. Majority carriers are pulled away from the junction in reverse bias and do not contribute to the small reverse current. Hence the statement in Reason R is false.

Therefore, the correct option is:

$\boxed{\text{Option C: A is true but R is false}}$

In this circuit, diode $ D_1 $ is reverse biased, meaning it does not conduct current. On the other hand, diode $ D_2 $ is forward biased, so it allows current to flow through it.

Due to this configuration, there is a current flowing through $ D_2 $, and a voltage drop of 5 V occurs across the resistor connected in the circuit. As a result, the output voltage ($ V_{\text{out}} $) is 0 V.

$\begin{aligned} & \mathrm{Y}_1=\mathrm{A} \cdot \mathrm{~B}, \mathrm{Y}_2=\overline{\mathrm{A}}+\mathrm{B} \\ & \mathrm{Y}=\overline{\mathrm{Y}_1 \cdot \mathrm{Y}_2}=\overline{\mathrm{Y}}_1+\overline{\mathrm{Y}}_2 \\ & \mathrm{Y}=\overline{\mathrm{A} \cdot \mathrm{~B}}+\overline{\overline{\mathrm{A}}+\mathrm{B}} \\ & \mathrm{Y}=\overline{\mathrm{A}}+\overline{\mathrm{B}}+\mathrm{A} \cdot \overline{\mathrm{~B}} \end{aligned}$

$\mathrm{V}_1=\frac{400}{100+400} \times 12 \mathrm{~V}=\frac{4}{5} \times 12=\frac{48}{5} \mathrm{~V}$

here, $\mathrm{V}_1>\mathrm{V}_{\mathrm{z}},\left(\mathrm{V}_{\mathrm{z}}=\right.$ Zener Voltage $)$

So, Zener breakdown will be take place So, voltage across $400 \Omega$ will be 4 V

$\mathrm{I}=\frac{4}{400} \mathrm{~A}=\frac{1}{100 \mathrm{~A}}=10 \mathrm{~mA}$

(A) n type semiconductor holes are minority carriers and $\mathrm{e}^{-}$are majority carriers

(B) Dopant are pentavalent atom.

(C) $\mathrm{n}_{\mathrm{e}} \cdot \mathrm{n}_{\mathrm{h}}=\mathrm{n}_{\mathrm{i}}^2$ for intrinsic semiconductor

(E) In $n$ type semiconductor primary source of holes generation are thermal excitation.

$\because \overline{\mathrm{A}} \cdot \overline{\mathrm{C}}+\overline{\mathrm{A}+\mathrm{C}} \equiv$ NOR gate

Only option (B) matches with the truth table.

From the circuit diagram,

$\begin{aligned} & 5 \mathrm{i}=\frac{20}{400}=\frac{1}{20} \mathrm{~A} \\ & \therefore \mathrm{i}=\frac{1}{100} \mathrm{~A}=10 \mathrm{~mA}=\text { Load current } \end{aligned}$

Also, $\mathrm{V}_{\mathrm{L}}=5 \mathrm{~V}$

$\therefore \mathrm{R}_{\mathrm{L}}=\frac{5}{10 \times 10^{-3}} \Omega=500 \Omega$

Hence, option 4 is correct.

$\Rightarrow \text { OR Gate }$

$Y = \overline {A.B + A.\overline B } = \overline {A(B + \overline B )} = \overline {AI} $

$ \Rightarrow Y = \overline A $

1.

(As $A\,.\,A = A$

Hence, option 1 is correct.

Statement A: The junction area of solar cell is made very narrow compared to a photo diode.

• Let's think about the purpose of a solar cell. Its main job is to collect as much sunlight as possible to generate electricity.

• To collect more light, it needs a larger surface area. Therefore, the $p-n$ junction of a solar cell is made with a very large area (typically a few square centimeters).

• This statement says the area is narrow, which is the opposite. So, statement A is Incorrect.

Statement B: Solar cells are not connected with any external bias.

• Remember, a solar cell is like a small battery. It generates an electromotive force (e.m.f.) or voltage when light shines on it. It gives power; it doesn't take power from an external battery to work.

• We don't apply any external bias to it. We simply connect a load, like a bulb, across it to use the electricity it produces.

• So, statement B is Correct.

Statement C: LED is made of lightly doped p-n junction.

• An LED (Light Emitting Diode) works by the recombination of electrons and holes at the junction. To get bright light, we need a very high rate of recombination.

• A high rate of recombination is only possible if there are a large number of electrons on the n-side and holes on the p-side.

• To achieve this high concentration of charge carriers, the $p-n$ junction of an LED is heavily doped, not lightly doped.

• So, statement C is Incorrect.

Statement D: Increase of forward current results in continuous increase of LED light intensity.

• It is true that the intensity of light from an LED increases as we increase the forward current. More current means more electrons and holes are crossing the junction and recombining per second, which produces more light.

• However, we cannot increase the current indefinitely. Every LED has a maximum current rating mentioned by the manufacturer. If we pass a current higher than this safe limit, the LED will overheat and get permanently damaged.

• So, the increase is not "continuous" without any limit.

• Therefore, this statement is Incorrect.

Statement E: LEDs have to be connected in forward bias for emission of light.

• This is the basic condition for an LED to work. When we connect it in forward bias, the potential barrier at the junction is lowered.

• This allows the majority carriers to flow across the junction and recombine. This recombination process releases energy in the form of light (photons).

• In reverse bias, the barrier height increases, very little current flows, and no light is emitted.

• So, statement E is Correct.

Final Conclusion:

Based on our step-by-step analysis, the only correct statements are B and E.

Looking at the options provided:

Option A: A, C, E Only

Option B: B, E Only

Option C: A, C Only

Option D: B, D, E Only

Thus, the correct choice is Option B.

To determine the current through the battery in this circuit, we need to consider the equivalent resistance and the biasing of the components involved.

Both components in the circuit are forward-biased. Given this, the equivalent resistance ($R_{\text{eq}}$) is $10 \, \Omega$.

The current ($i$) through the circuit can be calculated using Ohm's law:

$ i = \frac{V}{R} = \frac{5 \, \text{V}}{10 \, \Omega} = 0.5 \, \text{A} $

Thus, the current through the battery is $0.5 \, \text{A}$.

Current through ammeter $=1 \mathrm{~A}$

$ \mathrm{R}_{\text {net }}=6 \Omega $

$ \begin{aligned} & \mathrm{V}_{\mathrm{AB}}=0.5 \times 4=2 \mathrm{volt} \\ & \mathrm{~V}_{\mathrm{CD}}=1 \times 4=4 \mathrm{volt} \end{aligned} $

$\mathrm{A}, \mathrm{B} \& \mathrm{D}$ are correct

For NOR gate : $\overline{\mathrm{A}} \overline{\mathrm{B}}=\overrightarrow{\mathrm{A}}+\mathrm{B}$

$\therefore$ Truth table $ \begin{array}{ccc} \mathrm{A} & \mathrm{~B} & \mathrm{Y} \\ 0 & 0 & 1 \\ 0 & 1 & 1 \\ 1 & 0 & 0 \\ 1 & 1 & 1 \end{array}$

$\therefore$ Bonus

We know, if $V_A > V_B$ then diode is forward biased.

Hence, (B), (C) and (E) only.

$\begin{aligned} & Y=\overline{A B+\overline{A B}} \\ & \text { for } A=0, B=1, Y=1 \\ & \text { for } A=1, B=0, Y=1 \end{aligned}$

As this is a reverse bias characteristic. It should be for Zener diode working as voltage regulator.

The wavelength of light emitted by a Light Emitting Diode (LED) fabricated using a semiconducting material can be determined by the energy band gap of the material. The energy of the photon emitted, which corresponds to the band gap energy, is given by the equation:

$E = \frac{hc}{\lambda}$

Where:

• $E$ is the energy of the emitted photon (in joules when $h$ and $c$ are in SI units), corresponding to the band gap energy of the material.
• $h$ is Planck's constant ($6.626 \times 10^{-34} \, \mathrm{m^2\,kg/s}$).
• $c$ is the speed of light in vacuum ($3.0 \times 10^{8} \,\mathrm{m/s}$).
• $\lambda$ is the wavelength of the emitted light (in meters).

However, since the energy band gap given is in electronvolts (eV), and we are looking for the wavelength in nanometers (nm), we can use the energy formula directly in terms of eV and then do the unit conversion conveniently. The conversion between energy (in eV) and wavelength (in nm) without needing to convert eV to Joules is facilitated by the equation:

$\lambda(\mathrm{nm}) = \frac{1240}{E(\mathrm{eV})}$

Here, 1240 nm·eV is a conversion factor used for directly converting energy in eV to wavelength in nm.

Given the band gap energy of GaAs is $1.42 \mathrm{~eV}$, the wavelength ($\lambda$) of light emitted can be found as:

$\lambda = \frac{1240}{1.42} = 873.24 \mathrm{~nm}$

Thus, the wavelength of light emitted from the LED is approximately 873.24 nm, which is closest to:

Option B: 875 nm.

The energy required to create a hole in a p-type semiconductor can be directly related to the acceptor level because this energy level represents the minimum energy required to excite an electron from the valence band into the acceptor level, effectively creating a hole. The acceptor level is given as $6 \, \text{eV}$.

To find the maximum wavelength of light that can excite an electron into this level, we use the equation that relates the energy ($E$) of a photon to its wavelength ($\lambda$):

$E = \frac{hc}{\lambda}$

Where:

• $E$ is the energy in electronvolts (eV),
• $h$ is Planck's constant,
• $c$ is the speed of light, and
• $\lambda$ is the wavelength in nanometers (nm).

The product of $hc$ is given as $1242 \, \text{eV nm}$, allowing us to solve for $\lambda$ directly:

$\lambda = \frac{hc}{E}$

Substituting the given values:

$\lambda = \frac{1242 \, \text{eV nm}}{6 \, \text{eV}} = 207 \, \text{nm}$

Thus, the maximum wavelength of light that can create a hole in the semiconductor by exciting an electron into the acceptor level is $207 \, \text{nm}$. Therefore, the correct answer is Option D: 207 nm.

$\begin{aligned} Y & =(A+B)+(B \cdot 1) \\ & =A+B+B \\ & =A+B \end{aligned}$

For bulb to glow, there should be low-high combination across the bulb.

If $A=1, B=0, C=0$ & $D=0$

$\overline{\overline{1}+1}=0 \quad \& \quad \overline{0}=1$

So, bulb will glow.

In the given diagram, only the diode given in option (D) is forward bias, so this circuit can be used to measure dynamic resistance of p-n junction diode.

So, $Y=A+B$

Here $D_1$ is forward wise while $D_2$ is reversed wise

So net resistance between end, $R=\frac{15 \times 10}{25}=6 \Omega$